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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
| commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
| tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/supermicro/h8dmr/romstage.c | |
| parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) | |
| download | coreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz | |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/h8dmr/romstage.c')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr/romstage.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index fd0634ff62..3ef91c82bb 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -37,7 +37,7 @@ #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -98,7 +98,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -129,13 +129,13 @@ static void sio_setup(void) smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uart_init(); console_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); |