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author | Paul Menzel <paulepanter@users.sourceforge.net> | 2013-10-18 09:42:55 +0200 |
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committer | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2013-10-18 17:44:56 +0200 |
commit | 6a4e9b547a0e73fb48ee228357820fb3ba85cec2 (patch) | |
tree | 36f5602238822afed6f08967eba787c1d2853556 /src/mainboard/supermicro/h8dmr | |
parent | cd9abf95e7fe3d67f02e5e0197efa2688db83d22 (diff) | |
download | coreboot-6a4e9b547a0e73fb48ee228357820fb3ba85cec2.tar.xz |
get_bus_conf.c: reindent with indent
Change-Id: Ia0c37339aa69b92a1b518fa5e49adc4a7628ae5d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3979
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/supermicro/h8dmr')
-rw-r--r-- | src/mainboard/supermicro/h8dmr/get_bus_conf.c | 119 |
1 files changed, 60 insertions, 59 deletions
diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 5b16f83384..0279f8f7f6 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -31,19 +31,17 @@ #include <cpu/amd/amdk8_sysconf.h> #include <stdlib.h> - // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_mcp55[8]; //1 - unsigned apicid_mcp55; +unsigned char bus_mcp55[8]; //1 +unsigned apicid_mcp55; - unsigned char bus_pcix[3]; // under bus_mcp55_2 +unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - 0x0000ff0, - 0x0000ff0, +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not + //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + 0x0000ff0, + 0x0000ff0, // 0x0000ff0, // 0x0000ff0, // 0x0000ff0, @@ -51,8 +49,8 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most + +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, // 0x20202020, @@ -62,9 +60,8 @@ unsigned hcdnx[] = // 0x20202020, // 0x20202020, }; -unsigned sbdnb; - +unsigned sbdnb; static unsigned get_bus_conf_done = 0; @@ -74,71 +71,75 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; - int i; + device_t dev; + int i; - if(get_bus_conf_done==1) return; //do it only once + if (get_bus_conf_done == 1) + return; //do it only once - get_bus_conf_done = 1; + get_bus_conf_done = 1; - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); - for(i=0;i<sysconf.hc_possible_num; i++) { - sysconf.pci1234[i] = pci1234x[i]; - sysconf.hcdn[i] = hcdnx[i]; - } + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } - get_sblk_pci1234(); + get_sblk_pci1234(); - sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sbdn = sysconf.sbdn; - sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain + sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain - for(i=0; i<8; i++) { + for (i = 0; i < 8; i++) { bus_mcp55[i] = 0; } - for(i=0; i<3; i++) { + for (i = 0; i < 3; i++) { bus_pcix[i] = 0; } - bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; - /* MCP55 */ - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0)); - if (dev) { - bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_mcp55[2]++; - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06); - - bus_mcp55[1] = 2; - bus_mcp55[2] = 3; - } - - for(i=2; i<8;i++) { - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0)); - if (dev) { - bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 ); - } + /* MCP55 */ + dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0)); + if (dev) { + bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_mcp55[2]++; + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI 1:%02x.0, using defaults\n", + sbdn + 0x06); + + bus_mcp55[1] = 2; + bus_mcp55[2] = 3; + } + + for (i = 2; i < 8; i++) { + dev = + dev_find_slot(bus_mcp55[0], + PCI_DEVFN(sbdn + 0x0a + i - 2, 0)); + if (dev) { + bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, + "ERROR - could not find PCI %02x:%02x.0, using defaults\n", + bus_mcp55[0], sbdn + 0x0a + i - 2); } + } - if(bus_mcp55[2]) { - for(i=0;i<2; i++) { - dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i)); - if(dev) { - bus_pcix[0] = bus_mcp55[2]; - bus_pcix[i+1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } + if (bus_mcp55[2]) { + for (i = 0; i < 2; i++) { + dev = dev_find_slot(bus_mcp55[2], PCI_DEVFN(0, i)); + if (dev) { + bus_pcix[0] = bus_mcp55[2]; + bus_pcix[i + 1] = + pci_read_config8(dev, PCI_SECONDARY_BUS); } } - + } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS @@ -146,6 +147,6 @@ void get_bus_conf(void) #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif - apicid_mcp55 = apicid_base+0; + apicid_mcp55 = apicid_base + 0; } |