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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-05 15:48:38 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-06-05 10:17:35 +0200 |
| commit | 7748ee5ee188bf6b3846501b32a9ae82ccb8e853 (patch) | |
| tree | b795bbb255aeb0345f744fce4a41a0d433c0f01b /src/mainboard/supermicro/h8dmr | |
| parent | 98a915e2621df4885ba42f09502775f1f4a288b4 (diff) | |
| download | coreboot-7748ee5ee188bf6b3846501b32a9ae82ccb8e853.tar.xz | |
AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0
If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus
is the first to scan and it will be assigned with bus number 0.
If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range
of bus numbers instead of assigning consecutive numbers across all the links.
All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge.
Follow-up can easily drop this if we find this is dictated by architecture.
Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8366
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Diffstat (limited to 'src/mainboard/supermicro/h8dmr')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr/Kconfig | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index f85460be08..9efc5d2ee2 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -59,10 +60,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 |