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authorElyes HAOUAS <ehaouas@noos.fr>2014-07-21 08:07:19 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2014-07-24 12:43:01 +0200
commitaedcc10ad30f3fcc1397035876672d235418393f (patch)
treeb65ec6f8e964ba7cbd6866cc54e1cc415072c05c /src/mainboard/supermicro/h8dmr_fam10
parent643646075019816c6ae441f613426caaf7b0bd2e (diff)
downloadcoreboot-aedcc10ad30f3fcc1397035876672d235418393f.tar.xz
src/mainboard: Remove trailing whitespace
Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6308 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/supermicro/h8dmr_fam10')
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index cd185f3c39..b393c34465 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -130,10 +130,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo + 1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
@@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n",
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
@@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* show final fid and vid */
msr = rdmsr(0xc0010071);
- printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n",
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);
#endif