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| author | Xavi Drudis Ferran <xdrudis@tinet.cat> | 2011-02-26 23:29:44 +0000 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2011-02-26 23:29:44 +0000 |
| commit | 4c28a6f01870e017dbedb4a0bba1e91148077040 (patch) | |
| tree | bf45e9ef2d9d7755cdf70321ae371ab395b631d7 /src/mainboard/supermicro/h8dmr_fam10 | |
| parent | 837403dddf7b05b1a2b1a09a2cd57975484c7568 (diff) | |
| download | coreboot-4c28a6f01870e017dbedb4a0bba1e91148077040.tar.xz | |
Make AMD Fam10h CPU microcode updates optional in Expert mode
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/h8dmr_fam10')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 327ae36226..c949f26539 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -68,7 +68,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" + +#if CONFIG_UPDATE_CPU_MICROCODE #include "cpu/amd/model_10xxx/update_microcode.c" +#endif + #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -145,7 +149,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); +#if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); +#endif post_code(0x33); cpuSetAMDMSR(); |