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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-06-16 17:24:14 +1000
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-18 21:17:27 +0200
commitc94d73e0e6703369831fe6d489a20d71ab2bb974 (patch)
treec02321f3815f217665c57fd159fb43b2a1e47788 /src/mainboard/supermicro/h8qgi
parent401b8accf8fdade02f40f528812ac081c7a0f432 (diff)
downloadcoreboot-c94d73e0e6703369831fe6d489a20d71ab2bb974.tar.xz
mainboard: Clear up remaining SIO_PORT from Kconfig
Push back any board specific values back into romstage.c #defines and drop any remaining fragments of CONFIG_SIO_PORT in-tree. Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6045 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro/h8qgi')
-rw-r--r--src/mainboard/supermicro/h8qgi/Kconfig7
-rw-r--r--src/mainboard/supermicro/h8qgi/romstage.c6
2 files changed, 5 insertions, 8 deletions
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
index 44057ae497..ee78a2fbba 100644
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -72,13 +72,6 @@ config RAMBASE
hex
default 0x200000
-config SIO_PORT
- hex
- default 0x164E
- help
- though UARTs are on the NUVOTON BMC, port 0x164E
- PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
-
config DRIVERS_PS2_KEYBOARD
bool
default y
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index f9d3ba1a6e..d95db3c6f6 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -35,6 +35,10 @@
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
+/* though UARTs are on the NUVOTON BMC, port 0x164E
+ * PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
+ */
+#define SIO_PORT 0x164e
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -49,7 +53,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
- wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
+ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
post_code(0x34);