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| author | Zheng Bao <fishbaozi@gmail.com> | 2013-01-05 12:17:46 +0800 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2013-01-11 00:42:07 +0100 |
| commit | 105da50df4fe6073575a2eb6247d916746b6143e (patch) | |
| tree | a7c23555a675299e2ecd691abbc7d57ca1e7f80c /src/mainboard/supermicro/h8scm/Kconfig | |
| parent | 8a5ee9ce04cb88a57cf0a0d8a405c9865c99c01a (diff) | |
| download | coreboot-105da50df4fe6073575a2eb6247d916746b6143e.tar.xz | |
AMD: Set the mask of MTRR according to CONFIG_CPU_ADDR_BITS
The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these
bits will cause exception. So be carefull when spread this change.
The supermicro/h8scm needs more work. Currently it is set as it was.
We need to check if the F10 and F15 have different value.
Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro/h8scm/Kconfig')
| -rw-r--r-- | src/mainboard/supermicro/h8scm/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig index e7dae6618d..b93bfadcfc 100644 --- a/src/mainboard/supermicro/h8scm/Kconfig +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -59,6 +59,10 @@ config MAX_PHYSICAL_CPUS int default 16 +config CPU_ADDR_BITS + int + default 36 # TODO: Set it conservatively to match both fam10 & 15 + config HW_MEM_HOLE_SIZE_AUTO_INC bool default n |