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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-19 15:55:05 +0100 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-20 18:58:43 +0000 |
commit | f2e42c4a8ec75c162251c72df8ac3da12e8a3eb9 (patch) | |
tree | fd5851ba2be3965df592355d02bce01f7dab0215 /src/mainboard/supermicro/h8scm_fam10/mptable.c | |
parent | ad983eeec76ecdb2aff4fb47baeee95ade012225 (diff) | |
download | coreboot-f2e42c4a8ec75c162251c72df8ac3da12e8a3eb9.tar.xz |
mb/*/*: Drop AMDFAM10 mainboards
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/h8scm_fam10/mptable.c')
-rw-r--r-- | src/mainboard/supermicro/h8scm_fam10/mptable.c | 128 |
1 files changed, 0 insertions, 128 deletions
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c deleted file mode 100644 index 112d20ae41..0000000000 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <stdint.h> -#include <cpu/amd/amdfam10_sysconf.h> - -extern u8 bus_sr5650[14]; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u32 apicid_sp5100; - u32 apicid_sr5650; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - apicid_sp5100 = 0x20; - apicid_sr5650 = apicid_sp5100 + 1; - - mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ - { - struct device *dev; - u32 *dword; - u8 byte; - - dev = pcidev_on_root(0x14, 0); - if (dev) { - dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sp5100, 0x11, dword); - - /* Initialize interrupt mapping */ - /* aza */ - byte = pci_read_config8(dev, 0x63); - byte &= 0xf8; - byte |= 0; /* 0: INTA, ...., 7: INTH */ - pci_write_config8(dev, 0x63, byte); - - /* SATA */ - dword = (u32 *)((pci_read_config32(dev, 0xac) & - ~(7 << 26)) | (6 << 26)); - - /* dword |= 1 << 22; PIC and APIC co exists */ - pci_write_config32(dev, 0xac, (u32)dword); - - /* - * 00:12.0: PROG SATA : INT F - * 00:13.0: INTA USB_0 - * 00:13.1: INTB USB_1 - * 00:13.2: INTC USB_2 - * 00:13.3: INTD USB_3 - * 00:13.4: INTC USB_4 - * 00:13.5: INTD USB2 - * 00:14.1: INTA IDE - * 00:14.2: Prog HDA : INT E - * 00:14.5: INTB ACI - * 00:14.6: INTB MCI - */ - } - dev = pcidev_on_root(0, 0); - if (dev) { - pci_write_config32(dev, 0xF8, 0x1); - dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); - smp_write_ioapic(mc, apicid_sr5650, 0x11, dword); - } - } - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); - - mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); - - /* on board NIC & Slot PCIE. */ - /* configuration B doesnt need dev 5,6,7 */ - /* - * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11); - * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); - * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); - */ - smp_write_pci_intsrc(mc, mp_INT, 0, 2, 0, apicid_sr5650, 28); /* dev 2 */ - smp_write_pci_intsrc(mc, mp_INT, 0, 4, 0, apicid_sr5650, 28); /* dev 4 */ - smp_write_pci_intsrc(mc, mp_INT, 0, 12, 0, apicid_sr5650, 30); /* dev 11 */ - smp_write_pci_intsrc(mc, mp_INT, 0, 12, 0, apicid_sr5650, 30); /* dev 12 */ - - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[2], 0, 0, apicid_sr5650, 0); /* card behind dev2 */ - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[4], 0, 0, apicid_sr5650, 20); - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[4], 0, 1, apicid_sr5650, 21); /* NIC */ - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[11], 0, 0, apicid_sr5650, 8); - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[11], 0, 1, apicid_sr5650, 9); /* card behind dev11 */ - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[12], 0, 0, apicid_sr5650, 12); - smp_write_pci_intsrc(mc, mp_INT, bus_sr5650[12], 0, 1, apicid_sr5650, 13); /* card behind dev12 */ - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} |