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authorKevin Paul Herbert <kph@meraki.net>2014-12-24 18:43:20 -0800
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-15 08:50:22 +0100
commitbde6d309dfafe58732ec46314a2d4c08974b62d4 (patch)
tree17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/mainboard/supermicro/h8scm_fam10
parent4b10dec1a66122b515b2191f823d7fd379ec655f (diff)
downloadcoreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.tar.xz
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/supermicro/h8scm_fam10')
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/mptable.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index 84593fcf0d..860c417dc6 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -56,13 +56,13 @@ static void *smp_write_config_table(void *v)
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
- u32 dword;
+ u32 *dword;
u8 byte;
dev = dev_find_slot(0, //bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
if (dev) {
- dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100, 0x11, dword);
/* Initialize interrupt mapping */
@@ -73,11 +73,11 @@ static void *smp_write_config_table(void *v)
pci_write_config8(dev, 0x63, byte);
/* SATA */
- dword = pci_read_config32(dev, 0xac);
- dword &= ~(7 << 26);
- dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+ dword = (u32 *)((pci_read_config32(dev, 0xac) &
+ ~(7 << 26)) | (6 << 26));
+
/* dword |= 1<<22; PIC and APIC co exists */
- pci_write_config32(dev, 0xac, dword);
+ pci_write_config32(dev, 0xac, (u32)dword);
/*
* 00:12.0: PROG SATA : INT F
@@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v)
dev = dev_find_slot(0, PCI_DEVFN(0, 0));
if (dev) {
pci_write_config32(dev, 0xF8, 0x1);
- dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
smp_write_ioapic(mc, apicid_sp5100+1, 0x11, dword);
}
}