mainboard: Add Supermicro X10SLM+-F

This board runs well with coreboot. The documentation part of this
commit lists what works and what doesn't.

Tested with GRUB 2.02 as a payload, loading SeaBIOS 1.12.0 which then
boots FreeBSD 11.2. It has also been tested with GRUB directly booting
Debian GNU/Linux 9.6 (kernel 4.9).

Change-Id: I291573d4651bdffe24eb841033ea6189fcbf8502
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 133 insertions, 0 deletions

diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb
new file mode 100644
index 0000000000..434fb59f49
--- /dev/null
+++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb
@@ -0,0 +1,133 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
+##
+## This program is free software: you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation, either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/haswell
+
+	device cpu_cluster 0 on
+		chip cpu/intel/haswell
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x15d9 0x0803 inherit
+
+		device pci 00.0 on  end # Host bridge
+		device pci 01.0 on  end # PEG 10
+		device pci 01.1 on  end # PEG 11
+		device pci 02.0 off end # IGD
+		device pci 03.0 off end # Mini-HD audio
+
+		chip southbridge/intel/lynxpoint
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8a"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x85"
+
+			register "sata_ahci" = "1"
+			register "sata_port_map" = "0x3f"
+
+			register "gen1_dec" = "0x00000295" # Super I/O HWM
+
+			device pci 14.0 on  end # xHCI controller
+			device pci 16.0 on  end # Management Engine interface 1
+			device pci 16.1 on  end # Management Engine interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on  end # EHCI controller 2
+			device pci 1b.0 off end # HD audio controller
+			device pci 1c.0 on      # PCIe root port 1
+				device pci 00.0 on # ASPEED PCI-to-PCI bridge
+					device pci 00.0 on end # VGA controller
+				end
+			end
+			device pci 1c.1 off end # PCIe root port 2
+			device pci 1c.2 on      # PCIe root port 3
+				device pci 00.0 on # Intel I210 Gigabit Ethernet
+					subsystemid 0x15d9 0x1533
+				end
+			end
+			device pci 1c.3 on      # PCIe root port 4
+				device pci 00.0 on # Intel I210 Gigabit Ethernet
+					subsystemid 0x15d9 0x1533
+				end
+			end
+			device pci 1c.4 on  end # PCIe root port 5
+			device pci 1c.5 off end # PCIe root port 6
+			device pci 1c.6 off end # PCIe root port 7
+			device pci 1c.7 off end # PCIe root port 8
+			device pci 1d.0 on  end # EHCI controller 1
+			device pci 1f.0 on      # LPC bridge
+				chip superio/nuvoton/nct6776
+					device pnp 2e.0   off end # Floppy
+					device pnp 2e.1   off end # Parallel
+					device pnp 2e.2   on      # UART A
+						io  0x60 = 0x03f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3   on      # UART B
+						io  0x60 = 0x02f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.5   off end # PS/2 KBC
+					device pnp 2e.6   off end # CIR
+					device pnp 2e.7   off end # GPIO8
+					device pnp 2e.107 off end # GPIO9
+					device pnp 2e.8   off end # WDT
+					device pnp 2e.108 off end # GPIO0
+					device pnp 2e.208 off end # GPIOA
+					device pnp 2e.308 off end # GPIO base
+					device pnp 2e.109 off end # GPIO1
+					device pnp 2e.209 off end # GPIO2
+					device pnp 2e.309 off end # GPIO3
+					device pnp 2e.409 off end # GPIO4
+					device pnp 2e.509 off end # GPIO5
+					device pnp 2e.609 off end # GPIO6
+					device pnp 2e.709 off end # GPIO7
+					device pnp 2e.a   off end # ACPI
+					device pnp 2e.b   on      # HWM, LED
+						io  0x60 = 0x0290
+						io  0x62 = 0
+						irq 0x70 = 0
+					end
+					device pnp 2e.d   off end # VID
+					device pnp 2e.e   off end # CIR wake-up
+					device pnp 2e.f   off end # GPIO PP/OD
+					device pnp 2e.14  off end # SVID
+					device pnp 2e.16  off end # Deep sleep
+					device pnp 2e.17  off end # GPIOA
+				end
+			end
+			device pci 1f.2 on  end # SATA controller 1
+			device pci 1f.3 on  end # SMBus
+			device pci 1f.5 off end # SATA controller 2
+			device pci 1f.6 on  end # PCH thermal sensor
+		end
+	end
+end