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| author | Kevin Chiu <Kevin.Chiu@quantatw.com> | 2019-07-04 18:43:14 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-10 10:20:00 +0000 |
| commit | 808440e6b2f7b69bcb14cccddf27b1239e47a792 (patch) | |
| tree | 5146c7c9c7e74b2dae305d766d2677fc5a1c3901 /src/mainboard/supermicro/x10slm-f | |
| parent | ad1456f0d7c9fcfcf6ef78969cb0e1ac6f17739a (diff) | |
| download | coreboot-808440e6b2f7b69bcb14cccddf27b1239e47a792.tar.xz | |
mb/google/octopus: Remove LPDDR4 RAMID index 5,6 CH[1] only SKU
From Intel EDS: Table 3-5. LPDDR4 Configurations
CH00 CH01 CH10 CH11
"x32 BGA" "x32 BGA" "x32 BGA" "x32 BGA"
"x32 BGA" "x32 BGA" "Unpopulated" "Unpopulated"
CH[1](CH10/CH11) can't use alone without CH[0]
BUG=b:135498646,b:136694293
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Change-Id: I03af74301aad3e688c97992b37c59b20a4fff58a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34069
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x10slm-f')
0 files changed, 0 insertions, 0 deletions