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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-03-31 21:42:02 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-04-10 22:30:06 +0000 |
| commit | fd8de1860df9487cffb62bb2b657bd6e55b20596 (patch) | |
| tree | ac3ac7d9210d693fdec7feec5f06bea5df68f0ce /src/mainboard/supermicro/x11-lga1151-series/variants | |
| parent | a0722870a818bec8693911d836ba1bb703d9c676 (diff) | |
| download | coreboot-fd8de1860df9487cffb62bb2b657bd6e55b20596.tar.xz | |
src/mb: Remove unneeded spaces before/after tabs
Change-Id: I02979a0632a7b356985f96c3ba239daba178b4e3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39989
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro/x11-lga1151-series/variants')
| -rw-r--r-- | src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 76e684ce4d..80d2305590 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -12,11 +12,11 @@ chip soc/intel/skylake register "gen2_dec" = "0x000c0ca1" # IPMI KCS # PCIe configuration - register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 - register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 - register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 - register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 - register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA + register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 + register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 + register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 + register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 + register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA # USB configuration # USB0/1 |