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| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-16 00:31:44 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-16 00:31:44 +0000 |
| commit | d6532116c94c705c7e94a34ab2f046e431fb3682 (patch) | |
| tree | 6068b85e702f6eaf5b40fa273edfb9bfc4d155a1 /src/mainboard/supermicro/x6dhe_g/mptable.c | |
| parent | e46c1c85c90b6d263f951ab745a9fadd93041111 (diff) | |
| download | coreboot-d6532116c94c705c7e94a34ab2f046e431fb3682.tar.xz | |
zero warnings days: unify mp tables. fix warnings.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/x6dhe_g/mptable.c')
| -rw-r--r-- | src/mainboard/supermicro/x6dhe_g/mptable.c | 33 |
1 files changed, 10 insertions, 23 deletions
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index e3cdad31a1..c50fabb0f3 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "X6DHE "; struct mp_config_table *mc; unsigned char bus_num; @@ -43,11 +43,9 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); if (dev) { bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n"); - - bus_esb6300_2 = 6; + bus_esb6300_1 = 6; } /* esb6300_1 */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -55,33 +53,25 @@ static void *smp_write_config_table(void *v) bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - - bus_esb6300_1 = 7; + bus_esb6300_2 = 7; bus_isa = 8; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); if (dev) { bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n"); - bus_pxhd_1 = 2; } /* pxhd-2 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); if (dev) { bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - bus_pxhd_2 = 3; } } @@ -106,8 +96,7 @@ static void *smp_write_config_table(void *v) if (res) { smp_write_ioapic(mc, 0x04, 0x20, res->base); } - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev); } @@ -118,14 +107,12 @@ static void *smp_write_config_table(void *v) if (res) { smp_write_ioapic(mc, 0x05, 0x20, res->base); } - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev); } } - /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); @@ -182,7 +169,7 @@ static void *smp_write_config_table(void *v) smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x01); -#warning "FIXME verify I have the irqs handled for all of the risers" + /* FIXME verify I have the irqs handled for all of the risers */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |