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authorStefan Reinauer <stepan@coresystems.de>2010-03-31 14:34:40 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-31 14:34:40 +0000
commit5a1f5970857a5ad1fda0cf9d5945192408bf537b (patch)
treeb81a16a564c29788dcb6c306ea27855703d230de /src/mainboard/supermicro/x6dhr_ig
parentb8ac05d187c6cc4e777c96d39e075c5d97d93ffc (diff)
downloadcoreboot-5a1f5970857a5ad1fda0cf9d5945192408bf537b.tar.xz
This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and
makes include/console/console.h and console/console.c usable both in __PRE_RAM__ and coreboot_ram stages. While debugging this, I removed an indirection from the e7520 ram init code (same as we did on a couple of other chipsets, removes some register pressure from romcc) Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code in cache_as_ram.inc) Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro/x6dhr_ig')
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/romstage.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 7ddb2c46d7..a703d15277 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -8,7 +8,7 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
@@ -63,10 +63,12 @@ static void main(unsigned long bist)
static const struct mem_controller mch[] = {
{
.node_id = 0,
+ /*
.f0 = PCI_DEV(0, 0x00, 0),
.f1 = PCI_DEV(0, 0x00, 1),
.f2 = PCI_DEV(0, 0x00, 2),
.f3 = PCI_DEV(0, 0x00, 3),
+ */
.channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, },
.channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, },
}