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authorefdesign98 <efdesign98@gmail.com>2011-07-20 12:37:58 -0600
committerMarc Jones <marcj303@gmail.com>2011-07-22 00:20:59 +0200
commit00c8c4a31632150fa711493f39e727da950ebe9f (patch)
treef3bad2e78ddb6999ad551a73f05c049a266a14ab /src/mainboard/supermicro
parent09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff)
downloadcoreboot-00c8c4a31632150fa711493f39e727da950ebe9f.tar.xz
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She <shekairui@gmail.com> Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro')
-rwxr-xr-x[-rw-r--r--]src/mainboard/supermicro/h8scm_fam10/Kconfig2
-rwxr-xr-x[-rw-r--r--]src/mainboard/supermicro/h8scm_fam10/mainboard.c37
-rwxr-xr-x[-rw-r--r--]src/mainboard/supermicro/h8scm_fam10/romstage.c15
3 files changed, 11 insertions, 43 deletions
diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig
index e0547ab5f4..7742133dac 100644..100755
--- a/src/mainboard/supermicro/h8scm_fam10/Kconfig
+++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig
@@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
- select HAVE_MAINBOARD_RESOURCES
select HAVE_HARD_RESET
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
@@ -24,7 +23,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_2048
select RAMINIT_SYSINFO
select ENABLE_APIC_EXT_ID
- select GFXUMA
config MAINBOARD_DIR
string
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
index e6ed22b1a0..90b53357ad 100644..100755
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
@@ -29,9 +29,6 @@
#include <southbridge/amd/sr5650/cmn.h>
#include "chip.h"
-#define SMBUS_IO_BASE 0x6000
-
-uint64_t uma_memory_base, uma_memory_size;
void set_pcie_reset(void);
void set_pcie_dereset(void);
@@ -95,47 +92,17 @@ static void h8scm_enable(device_t dev)
printk
(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
__func__, msr2.lo, msr2.hi);
-#if (CONFIG_GFXUMA == 1)
-
- /* refer to UMA Size Consideration in 780 BDG. */
- switch (msr.lo) {
- case 0x10000000: /* 256M system memory */
- uma_memory_size = 0x4000000; /* 64M recommended UMA */
- break;
-
- case 0x20000000: /* 512M system memory */
- uma_memory_size = 0x8000000; /* 128M recommended UMA */
- break;
-
- default: /* 1GB and above system memory */
- uma_memory_size = 0x10000000; /* 256M recommended UMA */
- break;
- }
-#else
- /* TODO: TOP_MEM2 */
- uma_memory_size = 0;//0x8000000; /* 128M recommended UMA */
-#endif
- uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
- printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
- __func__, uma_memory_size, uma_memory_base);
set_pcie_dereset();
/* get_ide_dma66(); */
}
+#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
int add_mainboard_resources(struct lb_memory *mem)
{
- /* UMA is removed from system memory in the northbridge code, but
- * in some circumstances we want the memory mentioned as reserved.
- */
-#if (CONFIG_GFXUMA == 1)
- printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
- uma_memory_base, uma_memory_size);
- lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
- uma_memory_size);
-#endif
return 0;
}
+#endif
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD H8SCM Mainboard")
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 8101d2fad2..6e6e3940df 100644..100755
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -42,13 +42,14 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-#include "superio/nuvoton/wpcm450/early_init.c"
#include <usbdebug.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/sb700/early_setup.c"
-#include "southbridge/amd/sr5650/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "southbridge/amd/sr5650/sr5650.h"
+#include "superio/nuvoton/wpcm450/wpcm450.h"
#include "northbridge/amd/amdfam10/debug.c"
static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -57,7 +58,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl)
static int spd_read_byte(u32 device, u32 address)
{
- return smbus_read_byte(device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -102,7 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
- disable_pcie_bridge();
+ /* SR56x0 pcie bridges block pci_locate_device() before pcie training.
+ * disable all pcie bridges on SR56x0 to work around it
+ */
+ sr5650_disable_pcie_bridge();
sb7xx_51xx_lpc_port80();
}
@@ -181,7 +185,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
sr5650_early_setup();
- disable_pcie_bridge();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID