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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-03-27 22:49:18 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-01 22:53:55 +0200
commit22564088c7ac48cfe03a61451d8f9d4b08dbe8b4 (patch)
treecaaa569df5429ab92d88b42ca3d1781974eb5194 /src/mainboard/supermicro
parent3e91cffd894336c7ec802f0fc49e25e2a3b4efc6 (diff)
downloadcoreboot-22564088c7ac48cfe03a61451d8f9d4b08dbe8b4.tar.xz
mainboards/amdfam10: Copy DIMM information to cbmem after romstage
src/northbridge/amd/amdfam10: Add amdmct_cbmem_store_info() function. Change-Id: I07376e276e3e9e3247d2576a09e58780d32a3a76 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c2
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c2
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/romstage.c2
3 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 980437b201..e1707ac95e 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -238,6 +238,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cbmem_initialize_empty();
post_code(0x41);
+ amdmct_cbmem_store_info(sysinfo);
+
timestamp_add_now(TS_END_ROMSTAGE);
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 20522e10de..7a75159d06 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -301,6 +301,8 @@ post_code(0x40);
cbmem_initialize_empty();
post_code(0x41);
+ amdmct_cbmem_store_info(sysinfo);
+
timestamp_add_now(TS_END_ROMSTAGE);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 355cf820b7..4b6eeb68f8 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -222,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cbmem_initialize_empty();
post_code(0x41);
+ amdmct_cbmem_store_info(sysinfo);
+
/*
dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);