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authorStefan Reinauer <reinauer@chromium.org>2013-02-12 14:17:15 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-14 02:00:10 +0100
commit4aff4458f58398f54c248604694c7005294c1747 (patch)
treeeb3d9259255abc486a4d6d9eb53199b4d408053e /src/mainboard/supermicro
parentdc8259ce1d2e866f3133da49c1d6f4773f5698c1 (diff)
downloadcoreboot-4aff4458f58398f54c248604694c7005294c1747.tar.xz
sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only PCI specific in a particular (northbridge/cpu) implementation, but not by concept. As implementations and hardware change, be more generic about our naming. This will allow us to support non-PCI systems without adding new keywords. Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2376 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8dme/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/h8dmr/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/h8qgi/devicetree.cb4
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/h8scm/devicetree.cb4
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/devicetree.cb8
-rw-r--r--src/mainboard/supermicro/x6dai_g/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/x6dhe_g/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/devicetree.cb2
-rw-r--r--src/mainboard/supermicro/x7db8/devicetree.cb2
13 files changed, 18 insertions, 18 deletions
diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb
index 73a43e8271..0c8cf61722 100644
--- a/src/mainboard/supermicro/h8dme/devicetree.cb
+++ b/src/mainboard/supermicro/h8dme/devicetree.cb
@@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # Local APIC of the CPU
end
end
- device pci_domain 0 on # PCI domain
+ device domain 0 on # PCI domain
subsystemid 0x15d9 0x1511 inherit
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb
index 6c96ac0dea..3d1e994d2f 100644
--- a/src/mainboard/supermicro/h8dmr/devicetree.cb
+++ b/src/mainboard/supermicro/h8dmr/devicetree.cb
@@ -4,7 +4,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex
device lapic 0 on end # Local APIC of the CPU
end
end
- device pci_domain 0 on # PCI domain
+ device domain 0 on # PCI domain
subsystemid 0x15d9 0x1511 inherit
chip northbridge/amd/amdk8 # Northbridge / RAM controller
device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
index 6c4443f902..e7fe9e41ba 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
@@ -4,7 +4,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
device lapic 0 on end # Local APIC of the CPU
end
end
- device pci_domain 0 on # PCI domain
+ device domain 0 on # PCI domain
subsystemid 0x15d9 0x1511 inherit
chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
index 48797d56d9..8365346bc7 100644
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -23,7 +23,7 @@ chip northbridge/amd/agesa/family15/root_complex
#device lapic 0x10 on end #f10
end
end
- device pci_domain 0 on
+ device domain 0 on
subsystemid 0x15d9 0xab11 inherit #SuperMicro
chip northbridge/amd/agesa/family15 # CPU side of HT root complex
device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology
@@ -125,6 +125,6 @@ chip northbridge/amd/agesa/family15/root_complex
device pci 18.4 on end
device pci 18.5 on end #f15
end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
- end #pci_domain
+ end #domain
end #northbridge/amd/agesa/family15/root_complex
diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
index 56ba7b5395..d797beaba3 100644
--- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb
@@ -4,7 +4,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex
device lapic 0 on end # Local APIC of the CPU
end
end
- device pci_domain 0 on # PCI domain
+ device domain 0 on # PCI domain
subsystemid 0x15d9 0x1511 inherit
chip northbridge/amd/amdfam10 # Northbridge / RAM controller
device pci 18.0 on end
diff --git a/src/mainboard/supermicro/h8scm/devicetree.cb b/src/mainboard/supermicro/h8scm/devicetree.cb
index 5ade0af64c..6367392a82 100644
--- a/src/mainboard/supermicro/h8scm/devicetree.cb
+++ b/src/mainboard/supermicro/h8scm/devicetree.cb
@@ -22,7 +22,7 @@ chip northbridge/amd/agesa/family15/root_complex
device lapic 0x10 on end
end
end
- device pci_domain 0 on
+ device domain 0 on
subsystemid 0x15d9 0xab11 inherit #Supermicro
chip northbridge/amd/agesa/family15 # CPU side of HT root complex
device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology
@@ -122,6 +122,6 @@ chip northbridge/amd/agesa/family15/root_complex
device pci 18.4 on end
device pci 18.5 on end #f15
end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
- end #pci_domain
+ end #domain
end #northbridge/amd/agesa/family15/root_complex
diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
index 9aa4406faf..eb7ae1b0f7 100644
--- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
+++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb
@@ -9,7 +9,7 @@ chip northbridge/amd/amdfam10/root_complex
device lapic 0 on end
end
end
- device pci_domain 0 on
+ device domain 0 on
subsystemid 0x15d9 0x1511 inherit
chip northbridge/amd/amdfam10
##device pci 18.0 on end
@@ -104,9 +104,9 @@ chip northbridge/amd/amdfam10/root_complex
device pci 19.3 on end
device pci 19.4 on end
end
- end #pci_domain
+ end #domain
#for node 32 to node 63
-# device pci_domain 0 on
+# device domain 0 on
# chip northbridge/amd/amdfam10
# device pci 00.0 on end# northbridge
# device pci 00.0 on end
@@ -118,7 +118,7 @@ chip northbridge/amd/amdfam10/root_complex
# device pci 00.4 on end
# device pci 00.5 on end
# end
-# end #pci_domain
+# end #domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name
diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb
index e6201a811e..f39ca6cc91 100644
--- a/src/mainboard/supermicro/x6dai_g/devicetree.cb
+++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb
@@ -1,5 +1,5 @@
chip northbridge/intel/e7525 # mch
- device pci_domain 0 on
+ device domain 0 on
subsystemid 0x15d9 0x6780 inherit
chip southbridge/intel/esb6300 # esb6300
register "pirq_a_d" = "0x0b0a0a05"
diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
index 08c0751c00..dfe2e8836d 100644
--- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb
@@ -5,7 +5,7 @@ chip northbridge/intel/e7520 # MCH
device pnp 00.2 off end
device pnp 00.3 off end
end
- device pci_domain 0 on
+ device domain 0 on
subsystemid 0x15d9 0x6080 inherit
chip southbridge/intel/esb6300 # ESB6300
register "pirq_a_d" = "0x0b070a05"
diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
index ecfe0a00a3..c074fe8c1f 100644
--- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
@@ -5,7 +5,7 @@ chip northbridge/intel/e7520 # MCH
device pnp 00.2 off end
device pnp 00.3 off end
end
- device pci_domain 0 on
+ device domain 0 on
subsystemid 0x15d9 0x6080 inherit
chip southbridge/intel/i82801ex # ICH5R
register "pirq_a_d" = "0x0b070a05"
diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
index 6ada3b1341..1b54204ac8 100644
--- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
@@ -1,5 +1,5 @@
chip northbridge/intel/e7520 # mch
- device pci_domain 0 on
+ device domain 0 on
subsystemid 0x15d9 0x5580 inherit
chip southbridge/intel/i82801ex # i82801er
# USB ports
diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
index 3d9b644fd9..1ec6639268 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
+++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
@@ -1,5 +1,5 @@
chip northbridge/intel/e7520 # mch
- device pci_domain 0 on
+ device domain 0 on
subsystemid 0x15d9 0x5580 inherit
chip southbridge/intel/i82801ex # i82801er
# USB ports
diff --git a/src/mainboard/supermicro/x7db8/devicetree.cb b/src/mainboard/supermicro/x7db8/devicetree.cb
index 8949c54806..0a3fabb2fb 100644
--- a/src/mainboard/supermicro/x7db8/devicetree.cb
+++ b/src/mainboard/supermicro/x7db8/devicetree.cb
@@ -28,7 +28,7 @@ chip northbridge/intel/i5000
end
end
- device pci_domain 0 on
+ device domain 0 on
device pci 00.0 on # Host bridge
subsystemid 0x15d9 0x2017
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 06:14:55 +0000