summaryrefslogtreecommitdiff
path: root/src/mainboard/supermicro
diff options
context:
space:
mode:
authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-03-13 13:27:58 -0500
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-03-19 08:28:43 +0100
commit86f4ca5b4b99a799b403e61a90aa24d103fb7f2f (patch)
treedb0e317ff1a0bba502ba0fa7f748e9d8b8c99eb3 /src/mainboard/supermicro
parente24f7d37cef5acb71c070f934a74286efb6ee32e (diff)
downloadcoreboot-86f4ca5b4b99a799b403e61a90aa24d103fb7f2f.tar.xz
cpu/amd/model_10xxx: Add support for early cbmem
mainboards/amd/fam10: Initialize cbmem area after raminit When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE When GFXUMA is disabled, CBMEM is placed at TOM This matches the behaviour present before conversion to early CBMEM. The CBMEM location code implicitly assumes TOM does not change between romstage and ramstage. TOM is set by romstage raminit, and is never changed by romstage or ramstage afterward. As the CBMEM location is positioned at a specific offset from TOM that is known to both romstage and ramstage early CBMEM is safe on Fam10h systems. TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp tables from romstage and cbmem log tables from ramstage. Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8489 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c1
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c1
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/romstage.c1
3 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index bc1ca24334..461546528d 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ cbmem_initialize_empty();
post_code(0x41);
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 2be09bccac..c8ed2dfda1 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -292,6 +292,7 @@ post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ cbmem_initialize_empty();
post_code(0x41);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index eb38a29bca..4c6292f40f 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
+ cbmem_initialize_empty();
post_code(0x41);
/*