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authorPatrick Georgi <patrick.georgi@secunet.com>2012-11-20 11:53:47 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-27 23:51:52 +0100
commite135ac5a7ea69b6edcb89345019212f5de412b1e (patch)
tree408611a9f2846867f9731af53b1f08dd32eb6851 /src/mainboard/supermicro
parentbdc1816b2379bdf569ac6746172bba41e1307917 (diff)
downloadcoreboot-e135ac5a7ea69b6edcb89345019212f5de412b1e.tar.xz
Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8dme/ap_romstage.c1
-rw-r--r--src/mainboard/supermicro/h8dme/romstage.c1
-rw-r--r--src/mainboard/supermicro/h8dmr/ap_romstage.c1
-rw-r--r--src/mainboard/supermicro/h8dmr/romstage.c1
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c1
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c1
6 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c
index ebd0305bf9..2e9c5a9029 100644
--- a/src/mainboard/supermicro/h8dme/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dme/ap_romstage.c
@@ -37,7 +37,6 @@
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 989f2d8872..6f156bc39f 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -35,7 +35,6 @@
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c
index 62d796aa1c..d04775bba3 100644
--- a/src/mainboard/supermicro/h8dmr/ap_romstage.c
+++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c
@@ -37,7 +37,6 @@
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index cdef306dbc..e3113d85dc 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -38,7 +38,6 @@
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index ddd0920e77..be5a8e1874 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -37,7 +37,6 @@
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "cpu/amd/model_10xxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 2f5be994c8..28efb1cf87 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -37,7 +37,6 @@
#include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
-#include "cpu/amd/model_10xxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"