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authorAladyshev Konstantin <aladyshev@nicevt.ru>2012-12-18 23:15:55 +0400
committerRonald G. Minnich <rminnich@gmail.com>2012-12-21 15:43:38 +0100
commitec3daf7e08b4c42b45fc2c84b92820af6688e11b (patch)
treed79f3fa4ae3393d008f9515d7beda5858f732df8 /src/mainboard/supermicro
parent7299c139c508f64f1bfb3dd35bbe33688eada45c (diff)
downloadcoreboot-ec3daf7e08b4c42b45fc2c84b92820af6688e11b.tar.xz
Supermicro H8QGI: Fix routing from 16 to 55 in ACPI table
H8QGI board has 2 IO-APICS with 56 IRQ’s: IOAPIC[0]: GSI 0-23 - SB700 southbridge IOAPIC[1]: GSI 24-55 - RD890 northbridge `gDefaultApicDeviceInfoTable[]` structure in northbridge code vendorcode/amd/cimx/rd890/nbIoApic.c has IO-APIC interrupt mapping for HT and IOMMU set to last 31 IRQ pin (24+31=55). CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = { // Group Swizzling Port Int Pin {0, 0, 31}, //HT {0, 0, 31}, //IOMMU […] Also the same value (55) can be found in original Supermicro BIOS ACPI DSDT. Change-Id: Ie26da1f773716d1b7f5f5f884050ae799afc0b7e Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2047 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8qgi/acpi/routing.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
index 8bc06f6d0d..fb8996837f 100644
--- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
@@ -89,7 +89,7 @@ Scope(\_SB) {
Name(APR0, Package(){
/* NB devices in APIC mode */
/* Bus 0, Dev 0 - SR5650 HT */
- Package() { 0xFFFF, Zero, Zero, 16 },
+ Package() { 0xFFFF, Zero, Zero, 55 },
/* Bus 0, Dev 1 - CLKCONFIG */