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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-21 19:35:16 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-07-24 13:59:22 +0200
commit0c797f1c28cd16c64482b2cea554e89baaa31445 (patch)
tree0eb73249b03eb0609e350250c32b4f0bdab3bcaf /src/mainboard/supermicro
parent0ff17c9cae11b46535b99880f013d0ca084ea1f8 (diff)
downloadcoreboot-0c797f1c28cd16c64482b2cea554e89baaa31445.tar.xz
AGESA: Drop offset on PCI device enumeration
Integrated PCI devices in southbridge silicon have static BDFs, no need to have variables to store the parent bus or an offset with constant zero. Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8qgi/get_bus_conf.c4
-rw-r--r--src/mainboard/supermicro/h8qgi/irq_tables.c8
-rw-r--r--src/mainboard/supermicro/h8qgi/mptable.c3
-rw-r--r--src/mainboard/supermicro/h8scm/get_bus_conf.c4
-rw-r--r--src/mainboard/supermicro/h8scm/irq_tables.c8
-rw-r--r--src/mainboard/supermicro/h8scm/mptable.c3
6 files changed, 10 insertions, 20 deletions
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
index 549334e793..8531e697a9 100644
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
@@ -31,14 +31,12 @@
* and acpi_tables busnum is default.
*/
u8 bus_sp5100[2];
-u32 sbdn_sp5100;
void get_bus_conf(void)
{
device_t dev;
int i;
- sbdn_sp5100 = 0;
for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) {
bus_sp5100[i] = 0;
@@ -47,7 +45,7 @@ void get_bus_conf(void)
bus_sp5100[0] = 0;
/* sp5100 */
- dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev) {
bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c
index 6b1e226007..0af225c9dd 100644
--- a/src/mainboard/supermicro/h8qgi/irq_tables.c
+++ b/src/mainboard/supermicro/h8qgi/irq_tables.c
@@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_sp5100[2];
-extern unsigned long sbdn_sp5100;
unsigned long write_pirq_routing_table(unsigned long addr)
{
@@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_sp5100[0];
- pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4;
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
/* pci bridge */
- write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4,
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 754ed549bf..3793212711 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -29,7 +29,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sp5100[2];
-extern u32 sbdn_sp5100;
static void *smp_write_config_table(void *v)
{
@@ -59,7 +58,7 @@ static void *smp_write_config_table(void *v)
apicid_sp5100 = CONFIG_MAX_CPUS + 1;
apicid_sr5650 = apicid_sp5100 + 1;
- dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c
index 28c4bf7924..46ed054a26 100644
--- a/src/mainboard/supermicro/h8scm/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c
@@ -31,14 +31,12 @@
* and acpi_tables busnum is default.
*/
u8 bus_sp5100[2];
-u32 sbdn_sp5100;
void get_bus_conf(void)
{
device_t dev;
int i;
- sbdn_sp5100 = 0;
for (i = 0; i < 0; i++) {
bus_sp5100[i] = 0;
@@ -47,7 +45,7 @@ void get_bus_conf(void)
bus_sp5100[0] = 0;
/* sp5100 */
- dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4));
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
if (dev) {
bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
diff --git a/src/mainboard/supermicro/h8scm/irq_tables.c b/src/mainboard/supermicro/h8scm/irq_tables.c
index 9770e6d848..8f727563a7 100644
--- a/src/mainboard/supermicro/h8scm/irq_tables.c
+++ b/src/mainboard/supermicro/h8scm/irq_tables.c
@@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_sp5100[2];
-extern unsigned long sbdn_sp5100;
unsigned long write_pirq_routing_table(unsigned long addr)
{
@@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_sp5100[0];
- pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4;
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
pirq->exclusive_irqs = 0;
@@ -87,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
- write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4,
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c
index 754ed549bf..3793212711 100644
--- a/src/mainboard/supermicro/h8scm/mptable.c
+++ b/src/mainboard/supermicro/h8scm/mptable.c
@@ -29,7 +29,6 @@
#include <cpu/amd/amdfam10_sysconf.h>
extern u8 bus_sp5100[2];
-extern u32 sbdn_sp5100;
static void *smp_write_config_table(void *v)
{
@@ -59,7 +58,7 @@ static void *smp_write_config_table(void *v)
apicid_sp5100 = CONFIG_MAX_CPUS + 1;
apicid_sr5650 = apicid_sp5100 + 1;
- dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
+ dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
if (dev) {
/* Set SP5100 IOAPIC ID */
dword = pci_read_config32(dev, 0x74) & 0xfffffff0;