diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-21 17:29:59 +0000 |
commit | 57b2ff886e0ce2c92820f5722c8031def3ac94cf (patch) | |
tree | 3bf95eb33cd3de0b8f2bae495b3ae1453601c4d3 /src/mainboard/supermicro | |
parent | 5244e1ba63e5f3ea12066734bfb0d864a8f1f11d (diff) | |
download | coreboot-57b2ff886e0ce2c92820f5722c8031def3ac94cf.tar.xz |
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r-- | src/mainboard/supermicro/h8dme/romstage.c | 23 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr/romstage.c | 21 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 22 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 26 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dai_g/romstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g/romstage.c | 12 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g2/romstage.c | 9 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig/romstage.c | 12 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig2/romstage.c | 8 |
9 files changed, 13 insertions, 128 deletions
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index ecaa2f93e6..de3bc2c35f 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -29,36 +29,26 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> - #include <console/console.h> #include <lib.h> #include <spd.h> - #include <cpu/amd/model_fxx_rev.h> - -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdk8/debug.c" - #include "cpu/x86/mtrr/earlymtrr.c" - #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -136,20 +126,13 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" - #include "resourcemap.c" - #include "cpu/amd/dualcore/dualcore.c" - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - #include "cpu/amd/model_fxx/fidvid.c" - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -313,6 +296,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now - } - diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index dad1b9ea54..573f69eb30 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -32,36 +32,26 @@ #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> - #include <console/console.h> #include <lib.h> #include <spd.h> - #include <cpu/amd/model_fxx_rev.h> - -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdk8/debug.c" - #include "cpu/x86/mtrr/earlymtrr.c" - #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -81,20 +71,13 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" - #include "resourcemap.c" - #include "cpu/amd/dualcore/dualcore.c" - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - #include "cpu/amd/model_fxx/fidvid.c" - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 34837f2cbf..174a6cefcf 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -30,15 +30,11 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> - #include <console/console.h> #include <lib.h> #include <spd.h> - #include <cpu/amd/model_10xxx_rev.h> - -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include "cpu/amd/model_10xxx/apic_timer.c" @@ -47,19 +43,14 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdfam10/debug.c" - #include "cpu/x86/mtrr/earlymtrr.c" - #include "northbridge/amd/amdfam10/setup_resource_map.c" +#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -71,24 +62,16 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdfam10/amdfam10.h" - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" - #include "resourcemap.c" - #include "cpu/amd/quadcore/quadcore.c" - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" - - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -113,7 +96,6 @@ static void sio_setup(void) dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4); dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); - } static const u8 spd_addr[] = { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 5c0cab41ff..e77b139745 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -30,15 +30,11 @@ #include <device/pnp_def.h> #include <arch/romcc_io.h> #include <cpu/x86/lapic.h> - #include <console/console.h> #include <lib.h> #include <spd.h> - #include <cpu/amd/model_10xxx_rev.h> - -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include "cpu/amd/model_10xxx/apic_timer.c" @@ -47,19 +43,14 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "superio/winbond/w83627hf/w83627hf_early_init.c" - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdfam10/debug.c" - #include "cpu/x86/mtrr/earlymtrr.c" - #include "northbridge/amd/amdfam10/setup_resource_map.c" +#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" - static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 @@ -74,26 +65,16 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdfam10/amdfam10.h" - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" - #include "resourcemap.c" - #include "cpu/amd/quadcore/quadcore.c" - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" - - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -116,7 +97,6 @@ static void sio_setup(void) dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); - } static const u8 spd_addr[] = { @@ -317,6 +297,4 @@ post_code(0x40); // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x42); // Should never see this post code. - } - diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 6f3c671dc3..b95bbc9ebf 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -64,6 +64,7 @@ static void main(unsigned long bist) skip_romstage(); } } + /* Setup the console */ outb(0x87,0x2e); outb(0x87,0x2e); @@ -115,11 +116,4 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 - while(1) { - hlt(); - } -#endif } - diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 18d8b265b2..995234b808 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -46,10 +46,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -71,6 +67,7 @@ static void main(unsigned long bist) skip_romstage(); } } + /* Setup the console */ outb(0x87,0x2e); outb(0x87,0x2e); @@ -131,11 +128,4 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 - while(1) { - hlt(); - } -#endif } - diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index e8fcf306b7..eef04d4f28 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -55,7 +55,6 @@ static void main(unsigned long bist) */ .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, - } }; @@ -66,6 +65,7 @@ static void main(unsigned long bist) skip_romstage(); } } + /* Setup the console */ outb(0x87,0x2e); outb(0x87,0x2e); @@ -126,11 +126,4 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 - while(1) { - hlt(); - } -#endif } - diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 0a9af2d3bf..89429466cf 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -45,10 +45,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -70,6 +66,7 @@ static void main(unsigned long bist) skip_romstage(); } } + /* Setup the console */ outb(0x87,0x2e); outb(0x87,0x2e); @@ -131,11 +128,4 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 - while(1) { - hlt(); - } -#endif } - diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index efdacb5a5a..ba6ba914be 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -66,6 +66,7 @@ static void main(unsigned long bist) skip_romstage(); } } + /* Setup the console */ outb(0x87,0x2e); outb(0x87,0x2e); @@ -127,11 +128,4 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 - while(1) { - hlt(); - } -#endif } - |