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author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-06 18:17:01 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-06 18:17:01 +0000 |
commit | 9b9791c29d0f4e88127f59bb87d53cfed65cd912 (patch) | |
tree | 40ee30e72f4cfd015bafc59a642f1f69959a9d83 /src/mainboard/supermicro | |
parent | 29cb06abca665954e910f91397957ec93c627e86 (diff) | |
download | coreboot-9b9791c29d0f4e88127f59bb87d53cfed65cd912.tar.xz |
Winbond W83627HF: Use existing functions instead of open-coding.
Use w83627hf_set_clksel_48() where needed instead or open-coding the same
functionality, and also use w83627hf_enable_serial() instead of
w83627hf_enable_dev() (which does exactly the same, but isn't wrapped in the
enter/exit config mode functions).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6143 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r-- | src/mainboard/supermicro/h8dme/romstage.c | 7 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr/romstage.c | 7 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 7 | ||||
-rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 7 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dai_g/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhe_g/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig/romstage.c | 10 | ||||
-rw-r--r-- | src/mainboard/supermicro/x6dhr_ig2/romstage.c | 10 |
8 files changed, 28 insertions, 40 deletions
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index d11117f7d1..ff7b24f40e 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -48,6 +48,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -193,10 +194,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 4637392cd7..e7875956b2 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -51,6 +51,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -122,10 +123,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 43d4ff7e72..966ae3b694 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -50,6 +50,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -125,10 +126,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 95dd659b7f..d60350935d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -50,6 +50,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -176,10 +177,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 9ae30b0e0a..09e52873c1 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -16,13 +16,14 @@ #include "debug.c" #include "watchdog.c" #include "reset.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D1F0 | \ @@ -63,11 +64,8 @@ static void main(unsigned long bist) skip_romstage(); } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 1865a08dac..a6dfe502a2 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -17,13 +17,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhe_g_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D1F0 | \ @@ -60,11 +61,8 @@ static void main(unsigned long bist) skip_romstage(); } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 794234ea71..19527db918 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -15,13 +15,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhr_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D0F0 | \ @@ -59,11 +60,8 @@ static void main(unsigned long bist) skip_romstage(); } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 5e54fa66fa..eb54ef5632 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -15,13 +15,14 @@ #include "watchdog.c" #include "reset.c" #include "x6dhr2_fixups.c" -#include "superio/winbond/w83627hf/w83627hf_early_init.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define DEVPRES_CONFIG ( \ DEVPRES_D0F0 | \ @@ -59,11 +60,8 @@ static void main(unsigned long bist) skip_romstage(); } - /* Setup the console */ - outb(0x87,0x2e); - outb(0x87,0x2e); - pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + w83627hf_enable_serial(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); |