mb/supermicro/x11-lga1151-series: restructure and clean up devicetree

Drop zero-value devicetree options and move PcieRpEnable options down to
the corresponding devices.

Test: built with TIMELESS=1; binaries remain identical

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9285d786e973621a732e2627c734adc930e54207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

3 files changed, 9 insertions, 41 deletions

diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index e7b26dc5de..c021372fb9 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -1,10 +1,6 @@
 chip soc/intel/skylake
 
-	register "deep_s5_enable_ac" = "0"
-	register "deep_s5_enable_dc" = "0"
-
 	# FSP Configuration
-	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Disabled"
 
@@ -22,20 +18,6 @@ chip soc/intel/skylake
 		[7]	= 1, \
 	}"
 
-	register "SataPortsDevSlp" = "{\
-		[0]	= 0, \
-		[1]	= 0, \
-		[2]	= 0, \
-		[3]	= 0, \
-		[4]	= 0, \
-		[5]	= 0, \
-		[6]	= 0, \
-		[7]	= 0, \
-	}"
-
-	# superspeed_inter-chip_supplement (SSIC) disabled
-	register "SsicPortEnable" = "0"
-
 	# LPC
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
@@ -46,9 +28,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpSusMinAssert"	= "SLP_SUS_MIN_ASSERT_4S"
 	register "PmConfigSlpAMinAssert"	= "SLP_A_MIN_ASSERT_2S"
 
-	# No extra VR mailbox command
-	register "SendVrMbxCmd" = "0"
-
 	# Lock Down
 	register "common_soc_config" = "{
 	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
index 7996791a69..093786cbd5 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
@@ -11,19 +11,6 @@ chip soc/intel/skylake
 	register "gen1_dec" = "0x007c0a01"	# Super IO SWC
 	register "gen2_dec" = "0x000c0ca1"	# IPMI KCS
 
-	# PCIe configuration
-	# Enable JPCIE1
-	register "PcieRpEnable[0]" = "1"
-
-	# Enable ASpeed PCI bridge
-	register "PcieRpEnable[2]" = "1"
-
-	# Enable X550T (10GbE)
-	register "PcieRpEnable[4]" = "1"
-
-	# Enable M.2
-	register "PcieRpEnable[8]" = "1"
-
 	# FIXME: find out why FSP crashes without this
 	register "PchHdaVcType" = "Vc1"
 
@@ -66,9 +53,11 @@ chip soc/intel/skylake
 	device domain 0 on
 		device pci 01.0 on end	# unused
 		device pci 01.1 on	# PCIE Slot (JPCIE1)
+			register "PcieRpEnable[0]" = "1"
 			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
 		end
 		device pci 1c.0 on	# PCI Express Port 1 (Slot JPCIE1)
+			register "PcieRpEnable[2]" = "1"
 			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
 		end
 		device pci 1c.2 on	# PCI Express Port 3
@@ -77,10 +66,12 @@ chip soc/intel/skylake
 			end
 		end
 		device pci 1c.4 on	# PCI Express Port 5
+			register "PcieRpEnable[4]" = "1"
 			device pci 00.0 on end	# 10GbE
 			device pci 00.1 on end	# 10GbE
 		end
 		device pci 1d.0 on	# PCI Express Port 9
+			register "PcieRpEnable[8]" = "1"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
 		end
 		device pci 1f.0 on	# LPC Interface
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
index 8b0a2a0bd1..d7f187356f 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
@@ -11,13 +11,6 @@ chip soc/intel/skylake
 	register "gen1_dec" = "0x007c0a01"	# Super IO SWC
 	register "gen2_dec" = "0x000c0ca1"	# IPMI KCS
 
-	# PCIe configuration
-	register "PcieRpEnable[0]"	= "1"	# Enable PCH PCIe Port 1 / PCH SLOT4
-	register "PcieRpEnable[4]"	= "1"	# Enable PCH PCIe Port 5 / PCH SLOT5
-	register "PcieRpEnable[8]"	= "1"	# Enable PCH PCIe Port 9 / GbE 1
-	register "PcieRpEnable[9]"	= "1"	# Enable PCH PCIe Port 10 / GbE 2
-	register "PcieRpEnable[10]"	= "1"	# Enable PCH PCIe Port 11 / Aspeed 2400 VGA
-
 	# USB configuration
 	# USB0/1
 	register "usb2_ports[5]"	= "USB2_PORT_MID(OC2)"
@@ -58,18 +51,23 @@ chip soc/intel/skylake
 			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X"
 		end
 		device pci 1c.0 on	# PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4)
+			register "PcieRpEnable[0]" = "1"
 			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
 		end
 		device pci 1c.4 on	# PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5)
+			register "PcieRpEnable[4]" = "1"
 			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
 		end
 		device pci 1d.0 on	# PCH PCIe Port 9
+			register "PcieRpEnable[8]" = "1"
 			device pci 00.0 on end	# GbE 1
 		end
 		device pci 1d.1 on	# PCH PCIe Port 10
+			register "PcieRpEnable[9]" = "1"
 			device pci 00.1 on end	# GbE 2
 		end
 		device pci 1d.2 on	# PCH PCIe Port 11
+			register "PcieRpEnable[10]" = "1"
 			device pci 00.0 on	# Aspeed PCI Bridge
 				device pci 00.0 on end	# Aspeed 2400 VGA
 			end