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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-03 06:50:19 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-04 04:14:22 +0000
commit04d025cf5015b06f9e4dafc7092cfbd5d24b241e (patch)
tree05c5b7a4b4931faed61dfb84b86a759810f99be2 /src/mainboard/supermicro
parent8560db611608cbe0e344c1a301cf23e4c1fb36c8 (diff)
downloadcoreboot-04d025cf5015b06f9e4dafc7092cfbd5d24b241e.tar.xz
amdfam10: Declare get_sysinfo()
It's forbidden to use dereference CAR_GLOBAL variables directly. The notation fails after CAR teardown for romstage. Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33995 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c3
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c3
-rw-r--r--src/mainboard/supermicro/h8scm_fam10/romstage.c3
3 files changed, 3 insertions, 6 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index c6f5d63b9f..2750129859 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -48,7 +48,6 @@
#define SUPERIO_DEV PNP_DEV(0x2e, 0)
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
inline int spd_read_byte(unsigned int device, unsigned int address)
@@ -101,7 +100,7 @@ static const u8 spd_addr[] = {
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 87957e9443..56d9f35ef2 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -51,7 +51,6 @@
#define SMBUS_SWITCH2 0x72
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
void activate_spd_rom(const struct mem_controller *ctrl)
{
@@ -154,7 +153,7 @@ static void write_GPIO(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 93dca0293c..302e86f4e8 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -43,7 +43,6 @@
#include "cpu/amd/quadcore/quadcore.c"
int spd_read_byte(unsigned int device, unsigned int address);
-extern struct sys_info sysinfo_car;
int spd_read_byte(u32 device, u32 address)
@@ -53,7 +52,7 @@ int spd_read_byte(u32 device, u32 address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = &sysinfo_car;
+ struct sys_info *sysinfo = get_sysinfo();
static const u8 spd_addr[] = {
RC00, 0x52, 0x53, 0, 0, 0x50, 0x51, 0, 0,
//RC00, DIMM2, DIMM3, 0, 0, DIMM0, DIMM1, 0, 0,