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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-01 09:58:44 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-01 09:58:44 +0000 |
| commit | 6f56ad2d2ef6fbf9564123c5a9b64f05d006b2d7 (patch) | |
| tree | 43b0a727ae43ef41cc7bce9e4023ee48324ded8a /src/mainboard/supermicro | |
| parent | e4bc0f648067606841e5b24ed0bfe4d921838aec (diff) | |
| download | coreboot-6f56ad2d2ef6fbf9564123c5a9b64f05d006b2d7.tar.xz | |
Remove a couple of defines that seem to be the result of
copy&paste, without actually being used.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro')
| -rw-r--r-- | src/mainboard/supermicro/x6dai_g/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x6dhe_g/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x6dhe_g2/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x6dhr_ig/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/supermicro/x6dhr_ig2/romstage.c | 6 |
5 files changed, 0 insertions, 30 deletions
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 6f8ea1264f..6a7d77b3bd 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -21,9 +21,6 @@ #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -36,9 +33,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 745da9a059..64196b2fc5 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -22,9 +22,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -37,9 +34,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 6a2b2ea0c5..39cf5e778a 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -20,9 +20,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2) @@ -35,9 +32,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0708090a -#define RECVENB_CONFIG 0x0708090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 9d56f5c3ac..4dc5efe94a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -20,9 +20,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -36,9 +33,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index a0f6b4951c..6d8e482463 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -20,9 +20,6 @@ #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" -#define SIO_GPIO_BASE 0x680 -#define SIO_XBUS_BASE 0x4880 - #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -36,9 +33,6 @@ 0 ) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define RECVENA_CONFIG 0x0808090a -#define RECVENB_CONFIG 0x0808090a - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); |