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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-03-19 16:44:46 -0500 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-03-21 08:06:44 +0100 |
| commit | 91e9f676b779f3fc85efd0a5cac01a17cc66e01f (patch) | |
| tree | ef860cd3c7b106821f7805b49c61877259e49320 /src/mainboard/supermicro | |
| parent | a2a4bcf1a56f7d3041bf5dfff65ac9030ef1e3a0 (diff) | |
| download | coreboot-91e9f676b779f3fc85efd0a5cac01a17cc66e01f.tar.xz | |
mainboards/amd/fam10: Add romstage timestamps
Example output:
1:start of rom stage 542
2:before ram initialization 193,989 (193,447)
3:after ram initialization 3,319,114 (3,125,124)
4:end of romstage 3,320,004 (889)
Change-Id: Idcde7dc4c7a1d6c3118c82b67e8c2fcd4a07553b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8776
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro')
| -rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 9 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 8 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8scm_fam10/romstage.c | 9 |
3 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 461546528d..980437b201 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -30,6 +30,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> +#include <timestamp.h> #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> @@ -106,6 +107,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0, val, wants_reset; msr_t msr; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -226,11 +230,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); + cbmem_initialize_empty(); post_code(0x41); + timestamp_add_now(TS_END_ROMSTAGE); + post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 post_code(0x42); // Should never see this post code. } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index c8ed2dfda1..20522e10de 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -30,6 +30,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> +#include <timestamp.h> #include <lib.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> @@ -171,6 +172,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0, val, wants_reset; msr_t msr; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -290,11 +294,15 @@ post_code(0x3D); post_code(0x40); + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); + timestamp_add_now(TS_END_ROMSTAGE); + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x42); // Should never see this post code. } diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 4c6292f40f..355cf820b7 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -33,6 +33,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <console/console.h> +#include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> @@ -79,6 +80,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; msr_t msr; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -210,8 +214,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x40); + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); + cbmem_initialize_empty(); post_code(0x41); @@ -230,6 +237,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sr5650_before_pci_init(); sb7xx_51xx_before_pci_init(); + timestamp_add_now(TS_END_ROMSTAGE); + post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. |