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| author | Keith Hui <buurin@gmail.com> | 2017-09-01 19:55:49 -0400 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-21 15:29:49 +0000 |
| commit | aaa16fede70aaac56d1c835e663f52c4735826d8 (patch) | |
| tree | 35b72d736a61528999a2ccacb02480618acaa316 /src/mainboard/supermicro | |
| parent | 402276574b9812c0e2d527ed50a3392439a97919 (diff) | |
| download | coreboot-aaa16fede70aaac56d1c835e663f52c4735826d8.tar.xz | |
superio/winbond/*: Unify w*_set_clksel_48()
This function is identical throughout all Winbond superios in
the tree, so move it into superio/winbond/common/early_init.c,
renamed from early_serial.c because it now does more than just
early serial.
Change all affected mainboards to use the unified function.
Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/supermicro')
| -rw-r--r-- | src/mainboard/supermicro/h8dme/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8dmr/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index cacdd41b77..9deb940c4e 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 550bb8925a..9da1ab50ed 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index eb6edff249..7ba4f60241 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index edede81c09..3c255c5228 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); |