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authorKonstantin Aladyshev <aladyshev@nicevt.ru>2013-01-25 19:20:51 +0400
committerPatrick Georgi <patrick@georgi-clan.de>2013-02-11 08:27:51 +0100
commit3d990ffc88f5d54f32de28cc6a2a87f490bd701a (patch)
tree389177173d571a5e8f337b2c5e1ac9f3dfd2fcd4 /src/mainboard/supermicro
parent96e3035a1f9f6ade63d31c4f5e6f806df609f5c1 (diff)
downloadcoreboot-3d990ffc88f5d54f32de28cc6a2a87f490bd701a.tar.xz
Supermicro H8QGI: Substract 1 from MMCONF range limit
MMCONF space is defined by two config parameters: MMCONF_BASE_ADDRESS (0xF800 0000) MMCONF_BUS_NUMBER (64) Coreboot allocates 1MB per bus, so MMCONF limit should be: 0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF Current code does not have (-1) component, this makes MMCONF limit equal 0xFC00 FFFF. Not 0xFC00 0000, because according to BKDG lower two bytes of MMIO limit always equal 0xFFFF: MMIOLimit = {MMIOLimitRegister[47:16], FFFFh}. Add (-1) to correct this issue. No functionality change has been experienced. The five times slower RAM speed compared to the proprietary vendor BIOS still remains. Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9 Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru> Reviewed-on: http://review.coreboot.org/2193 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8qgi/agesawrapper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 9720bed4e9..517e1363f0 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -147,7 +147,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
* coreboot not implemente the range by range setting yet.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
- PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
+ PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
PciData = (PciData >> 8) & 0xFFFFFF00;
PciData |= 0x80; //NP
PciData |= sblink << 4;