zero warning days. Move RAMTOP and RAMBASE together.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 20 insertions, 29 deletions

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 25d60b37ff..5b158e0f56 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -85,12 +85,7 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
 
-static int smbus_send_byte_one(unsigned device, unsigned char val)
-{
-	return do_smbus_send_byte(SMBUS1_IO_BASE, device, val);
-}
-
-static void dump_smbus_registers(void)
+static inline void dump_smbus_registers(void)
 {
 	u32 device;
 
@@ -119,17 +114,22 @@ static void dump_smbus_registers(void)
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
-/* We don't do any switching yet.
+#if 0
+/* We don't do any switching yet. */
 #define SMBUS_SWITCH1 0x48
 #define SMBUS_SWITCH2 0x49
 	unsigned device=(ctrl->channel0[0])>>8;
 	smbus_send_byte(SMBUS_SWITCH1, device);
 	smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
-*/
-	/* nothing to do */
+#endif
+}
+
+#if 0
+static int smbus_send_byte_one(unsigned device, unsigned char val)
+{
+	return do_smbus_send_byte(SMBUS1_IO_BASE, device, val);
 }
 
-/*
 static inline void change_i2c_mux(unsigned device)
 {
 #define SMBUS_SWITCH1 0x48
@@ -146,7 +146,7 @@ static inline void change_i2c_mux(unsigned device)
         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
 	dump_smbus_registers();
 }
-*/
+#endif
 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
@@ -188,8 +188,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-
-	u32 value;
 	uint32_t dword;
 	uint8_t byte;
 
@@ -208,7 +206,6 @@ static void sio_setup(void)
 	dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
 	dword |= (1 << 16);
 	pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
-
 }
 
 /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */
@@ -222,20 +219,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    memory on each CPU must be an exact match.
  */
 	static const uint16_t spd_addr[] = {
+		// Node 0
 		RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2,
 		    RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6,
 		RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3,
 		    RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+		// Node 1
 		RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2,
 		    RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6,
 		RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3,
 		    RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7,
-#endif
 	};
 
-	struct sys_info *sysinfo =
-	    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	int needs_reset = 0;
 	unsigned bsp_apicid = 0;
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 24cc38f0fa..3dc8e30ef2 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -133,8 +133,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-
-        unsigned value;
         uint32_t dword;
         uint8_t byte;
         enable_smbus();
@@ -152,21 +150,21 @@ static void sio_setup(void)
         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
         dword |= (1<<16);
         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr [] = {
+			// Node 0
 			(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 			(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+			// Node 1
 			(0xa<<3)|4, (0xa<<3)|6, 0, 0,
 			(0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
 	};
 
-        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+        struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset = 0;
         unsigned bsp_apicid = 0;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index b1c20332cd..a60a4a610a 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -116,8 +116,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-
-        unsigned value;
         uint32_t dword;
         uint8_t byte;
         enable_smbus();
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index d762567717..e17614bbf1 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -120,8 +120,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-
-        unsigned value;
         uint32_t dword;
         uint8_t byte;
         enable_smbus();
@@ -149,7 +147,7 @@ static void sio_setup(void)
 #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
 #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
 #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
-void write_GPIO(void)
+static void write_GPIO(void)
 {
 	pnp_enter_ext_func_mode(GPIO1_DEV);
 	pnp_set_logical_device(GPIO1_DEV);