diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
| commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
| tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/supermicro | |
| parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) | |
| download | coreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz | |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro')
57 files changed, 495 insertions, 495 deletions
diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index f44677118c..1948784761 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -1,7 +1,7 @@ choice prompt "Mainboard model" depends on VENDOR_SUPERMICRO - + source "src/mainboard/supermicro/h8dme/Kconfig" source "src/mainboard/supermicro/h8dmr/Kconfig" source "src/mainboard/supermicro/h8dmr_fam10/Kconfig" diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index 60dd1b275e..3454cae313 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/supermicro/h8dme/cmos.layout b/src/mainboard/supermicro/h8dme/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dme/cmos.layout +++ b/src/mainboard/supermicro/h8dme/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb index 5d6776a3f2..f6f75efb65 100644 --- a/src/mainboard/supermicro/h8dme/devicetree.cb +++ b/src/mainboard/supermicro/h8dme/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdk8/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -67,24 +67,24 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -116,15 +116,15 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -135,5 +135,5 @@ chip northbridge/amd/amdk8/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 3a9218ba6c..5052f35d7b 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -40,7 +40,7 @@ unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -52,7 +52,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -98,7 +98,7 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_mcp55[i] = 0; } - + for(i=0; i<3; i++) { bus_pcix[i] = 0; } @@ -142,13 +142,13 @@ void get_bus_conf(void) } } } - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_mcp55 = apicid_base+0; diff --git a/src/mainboard/supermicro/h8dme/irq_tables.c b/src/mainboard/supermicro/h8dme/irq_tables.c index 5cb6d8420c..bc6aded97f 100644 --- a/src/mainboard/supermicro/h8dme/irq_tables.c +++ b/src/mainboard/supermicro/h8dme/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -33,11 +33,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index c7e46f2bda..8146923ef7 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1); @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) } - if(bus_pcix[0]) { + if(bus_pcix[0]) { for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } for(i=0;i<4;i++) { diff --git a/src/mainboard/supermicro/h8dme/resourcemap.c b/src/mainboard/supermicro/h8dme/resourcemap.c index fa22ee337b..db5d5fe185 100644 --- a/src/mainboard/supermicro/h8dme/resourcemap.c +++ b/src/mainboard/supermicro/h8dme/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index 60dd1b275e..3454cae313 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -25,7 +25,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 -#define SET_NB_CFG_54 1 +#define SET_NB_CFG_54 1 //used by raminit #define QRANK_DIMM_SUPPORT 1 diff --git a/src/mainboard/supermicro/h8dmr/cmos.layout b/src/mainboard/supermicro/h8dmr/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dmr/cmos.layout +++ b/src/mainboard/supermicro/h8dmr/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb index d83f00637d..67920c4657 100644 --- a/src/mainboard/supermicro/h8dmr/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdk8/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -56,29 +56,29 @@ chip northbridge/amd/amdk8/root_complex end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end + device i2c 50 on end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? @@ -87,24 +87,24 @@ chip northbridge/amd/amdk8/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -136,15 +136,15 @@ chip northbridge/amd/amdk8/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -155,5 +155,5 @@ chip northbridge/amd/amdk8/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 3a9218ba6c..5052f35d7b 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -40,7 +40,7 @@ unsigned char bus_pcix[3]; // under bus_mcp55_2 -unsigned pci1234x[] = +unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, @@ -52,7 +52,7 @@ unsigned pci1234x[] = // 0x0000ff0, // 0x0000ff0 }; -unsigned hcdnx[] = +unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, @@ -98,7 +98,7 @@ void get_bus_conf(void) for(i=0; i<8; i++) { bus_mcp55[i] = 0; } - + for(i=0; i<3; i++) { bus_pcix[i] = 0; } @@ -142,13 +142,13 @@ void get_bus_conf(void) } } } - + /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); -#else - apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif apicid_mcp55 = apicid_base+0; diff --git a/src/mainboard/supermicro/h8dmr/irq_tables.c b/src/mainboard/supermicro/h8dmr/irq_tables.c index 5cb6d8420c..bc6aded97f 100644 --- a/src/mainboard/supermicro/h8dmr/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! (but if you do, please run checkpir on it to verify) Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -33,11 +33,11 @@ #include <cpu/amd/amdk8_sysconf.h> -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -79,15 +79,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -100,11 +100,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - - pirq->size = 32 + 16 * slot_num; + + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index c7e46f2bda..8146923ef7 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -102,7 +102,7 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_mcp55, 0x1); @@ -144,9 +144,9 @@ static void *smp_write_config_table(void *v) } - if(bus_pcix[0]) { + if(bus_pcix[0]) { for(i=0;i<2;i++) { - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } for(i=0;i<4;i++) { diff --git a/src/mainboard/supermicro/h8dmr/resourcemap.c b/src/mainboard/supermicro/h8dmr/resourcemap.c index fa22ee337b..db5d5fe185 100644 --- a/src/mainboard/supermicro/h8dmr/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, @@ -217,7 +217,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -225,7 +225,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033, @@ -270,9 +270,9 @@ static void setup_mb_resource_map(void) * This field defines the highest bus number in configuration region i */ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index fd0634ff62..3ef91c82bb 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -37,7 +37,7 @@ #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif - + #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -98,7 +98,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -129,13 +129,13 @@ static void sio_setup(void) smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uart_init(); console_init(); - + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index 8d8936c92f..c142dcb290 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on + device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdfam10/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -56,29 +56,29 @@ chip northbridge/amd/amdfam10/root_complex end device pci 1.1 on # SM 0 chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end + device i2c 50 on end + end chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end - end + end chip drivers/generic/generic #dimm 0-1-0 device i2c 52 on end - end + end chip drivers/generic/generic #dimm 0-1-1 device i2c 53 on end - end + end chip drivers/generic/generic #dimm 1-0-0 device i2c 54 on end - end + end chip drivers/generic/generic #dimm 1-0-1 device i2c 55 on end - end + end chip drivers/generic/generic #dimm 1-1-0 device i2c 56 on end - end + end chip drivers/generic/generic #dimm 1-1-1 device i2c 57 on end - end + end end # SM device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? @@ -87,24 +87,24 @@ chip northbridge/amd/amdfam10/root_complex # end # chip drivers/generic/generic #PCIXB Slot1 # device i2c 51 on end -# end +# end # chip drivers/generic/generic #PCIXB Slot2 # device i2c 52 on end -# end +# end # chip drivers/generic/generic #PCI Slot1 # device i2c 53 on end -# end +# end # chip drivers/generic/generic #Master MCP55 PCI-E # device i2c 54 on end -# end +# end # chip drivers/generic/generic #Slave MCP55 PCI-E # device i2c 55 on end -# end +# end chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -136,7 +136,7 @@ chip northbridge/amd/amdfam10/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -147,10 +147,10 @@ chip northbridge/amd/amdfam10/root_complex device pci 19.3 on end device pci 19.4 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -161,5 +161,5 @@ chip northbridge/amd/amdfam10/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c index 673db742fb..a981fe1b9c 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8dmr_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0370; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h index 83f9dbab28..a2e6fc7ade 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; }; diff --git a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c index 13ae166708..0aded2ccbd 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8dmr_fam10/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -218,7 +218,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -273,9 +273,9 @@ static void setup_mb_resource_map(void) */ // WARD CHANGED PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index 9d37e2bba6..518f9458b6 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -1,23 +1,23 @@ -## +## ## This file is part of the coreboot project. -## +## ## Copyright (C) 2007 AMD ## Written by Yinghai Lu <yinghailu@amd.com> for AMD. -## +## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by ## the Free Software Foundation; either version 2 of the License, or ## (at your option) any later version. -## +## ## This program is distributed in the hope that it will be useful, ## but WITHOUT ANY WARRANTY; without even the implied warranty of ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. -## +## ## You should have received a copy of the GNU General Public License ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## +## entries diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 51c2feb000..5759f40ccf 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -8,9 +8,9 @@ chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10 #mc0 device pci 18.0 on end device pci 18.0 on end - device pci 18.0 on + device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 + chip southbridge/nvidia/mcp55 device pci 0.0 on end # HT device pci 1.0 on # LPC chip superio/winbond/w83627hf @@ -37,14 +37,14 @@ chip northbridge/amd/amdfam10/root_complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off # SFI + device pnp 2e.6 off # SFI io 0x62 = 0x100 end device pnp 2e.7 off # GPIO_GAME_MIDI io 0x60 = 0x220 io 0x62 = 0x300 irq 0x70 = 9 - end + end device pnp 2e.8 off end # WDTO_PLED device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.a off end # ACPI @@ -57,12 +57,12 @@ chip northbridge/amd/amdfam10/root_complex device pci 1.1 on end device pci 1.1 on # SM 1 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# +# chip drivers/generic/generic #MAC EEPROM device i2c 51 on end - end + end - end # SM + end # SM device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # IDE @@ -70,7 +70,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 device pci 6.1 off end # AZA - device pci 7.0 on + device pci 7.0 on device pci 1.0 on end end device pci 8.0 off end @@ -87,7 +87,7 @@ chip northbridge/amd/amdfam10/root_complex register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_addr" = "0x51" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end @@ -110,10 +110,10 @@ chip northbridge/amd/amdfam10/root_complex device pci 19.3 on end device pci 19.4 on end end # mc0 - + end # PCI domain - -# chip drivers/generic/debug + +# chip drivers/generic/debug # device pnp 0.0 off end # chip name # device pnp 0.1 on end # pci_regs_all # device pnp 0.2 off end # mem @@ -124,5 +124,5 @@ chip northbridge/amd/amdfam10/root_complex # device pnp 0.7 off end # tsc # device pnp 0.8 off end # io # device pnp 0.9 on end # io -# end +# end end #root_complex diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c index efaf4cb754..9338d5e08c 100644 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c @@ -19,7 +19,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This file was generated by getpir.c, do not modify! +/* This file was generated by getpir.c, do not modify! * (but if you do, please run checkpir on it to verify) * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up @@ -34,11 +34,11 @@ #include <cpu/amd/amdfam10_sysconf.h> #include "mb_sysconf.h" -static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, +static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t slot, uint8_t rfu) { - pirq_info->bus = bus; + pirq_info->bus = bus; pirq_info->devfn = devfn; pirq_info->irq[0].link = link0; pirq_info->irq[0].bitmap = bitmap0; @@ -80,15 +80,15 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq = (void *)(addr); v = (uint8_t *)(addr); - + pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - + pirq->rtr_bus = m->bus_mcp55[0]; pirq->rtr_devfn = ((sbdn+6)<<3)|0; pirq->exclusive_irqs = 0; - + pirq->rtr_vendor = 0x10de; pirq->rtr_device = 0x0364; @@ -101,7 +101,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) //pci bridge write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0x4ca0, 0x2, 0x4ca0, 0x3, 0x4ca0, 0x4, 0x4ca0, 0, 0); pirq_info++; slot_num++; - + for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; @@ -120,10 +120,10 @@ unsigned long write_pirq_routing_table(unsigned long addr) } #endif - pirq->size = 32 + 16 * slot_num; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) - sum += v[i]; + sum += v[i]; sum = pirq->checksum - sum; diff --git a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h index 42969bb71e..5a17fa9442 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h @@ -26,7 +26,7 @@ struct mb_sysconf_t { unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; + unsigned bus_type[256]; unsigned char bus_8132_0; //7 unsigned char bus_8132_1; //8 diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 551ee977fa..c365ddbe2d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -100,33 +100,33 @@ static void *smp_write_config_table(void *v) } - + /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6); + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); - - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ + + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/ - + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/ - for(j=7;j>=2; j--) { + for(j=7;j>=2; j--) { if(!m->bus_mcp55[j]) continue; for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); diff --git a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c index 13ae166708..0aded2ccbd 100644 --- a/src/mainboard/supermicro/h8qme_fam10/resourcemap.c +++ b/src/mainboard/supermicro/h8qme_fam10/resourcemap.c @@ -161,7 +161,7 @@ static void setup_mb_resource_map(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, @@ -218,7 +218,7 @@ static void setup_mb_resource_map(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ // WARD CHANGED @@ -273,9 +273,9 @@ static void setup_mb_resource_map(void) */ // WARD CHANGED PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x3f000203, /* link 2 of cpu 0 --> Nvidia MCP55 Pro */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index aa2081f7df..0d1657a170 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -93,12 +93,12 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #define MCP55_NUM 1 -#define MCP55_USE_NIC 0 +#define MCP55_USE_NIC 0 #define MCP55_USE_AZA 0 #define MCP55_PCI_E_X_0 4 @@ -128,13 +128,13 @@ static void sio_setup(void) smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; + byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); @@ -206,7 +206,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x30); - + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } diff --git a/src/mainboard/supermicro/x6dai_g/debug.c b/src/mainboard/supermicro/x6dai_g/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dai_g/debug.c +++ b/src/mainboard/supermicro/x6dai_g/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dai_g/devicetree.cb b/src/mainboard/supermicro/x6dai_g/devicetree.cb index 97176b9b78..038964e9ad 100644 --- a/src/mainboard/supermicro/x6dai_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dai_g/devicetree.cb @@ -1,20 +1,20 @@ chip northbridge/intel/e7525 # mch device pci_domain 0 on - chip southbridge/intel/esb6300 # esb6300 + chip southbridge/intel/esb6300 # esb6300 register "pirq_a_d" = "0x0b0a0a05" register "pirq_e_h" = "0x0a0b0c80" - + device pci 1c.0 on end - + device pci 1d.0 on end device pci 1d.1 on end device pci 1d.4 on end device pci 1d.5 on end device pci 1d.7 on end - + device pci 1e.0 on end - - device pci 1f.0 on + + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end device pnp 2e.1 off end @@ -45,7 +45,7 @@ chip northbridge/intel/e7525 # mch device pci 1f.6 on end end device pci 00.0 on end - device pci 00.1 on end + device pci 00.1 on end device pci 00.2 on end device pci 02.0 on end device pci 03.0 on end diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index a3bb398fa2..a0c863cb45 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) bus_isa = 6; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index b718daf9ab..da5cadac00 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -116,7 +116,7 @@ static void main(unsigned long bist) // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -127,8 +127,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c index 2531bc2969..1b1162c00d 100644 --- a/src/mainboard/supermicro/x6dai_g/watchdog.c +++ b/src/mainboard/supermicro/x6dai_g/watchdog.c @@ -18,17 +18,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); diff --git a/src/mainboard/supermicro/x6dhe_g/debug.c b/src/mainboard/supermicro/x6dhe_g/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhe_g/debug.c +++ b/src/mainboard/supermicro/x6dhe_g/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhe_g/devicetree.cb b/src/mainboard/supermicro/x6dhe_g/devicetree.cb index d5625e4c7c..075acfc232 100644 --- a/src/mainboard/supermicro/x6dhe_g/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g/devicetree.cb @@ -10,8 +10,8 @@ chip northbridge/intel/e7520 # MCH register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" - device pci 1c.0 on - chip drivers/generic/generic + device pci 1c.0 on + chip drivers/generic/generic device pci 01.0 on end # onboard gige1 device pci 02.0 on end # onboard gige2 end @@ -25,9 +25,9 @@ chip northbridge/intel/e7520 # MCH device pci 1d.7 on end # VGA / PCI 32-bit - device pci 1e.0 on + device pci 1e.0 on chip drivers/generic/generic - device pci 01.0 on end + device pci 01.0 on end end end @@ -35,7 +35,7 @@ chip northbridge/intel/e7520 # MCH device pci 1f.0 on # ISA bridge chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -62,17 +62,17 @@ chip northbridge/intel/e7520 # MCH device pci 00.0 on end # Northbridge device pci 00.1 on end # Northbridge Error reporting device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge device pci 00.1 on end # I/O apic device pci 00.2 on end # bridge device pci 00.3 on end # I/O apic end end -# device register "intrline" = "0x00070105" - device pci 04.0 on end - device pci 06.0 on end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end end device apic_cluster 0 on diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index c50fabb0f3..81ccf85458 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) bus_pxhd_2 = 3; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -162,7 +162,7 @@ static void *smp_write_config_table(void *v) bus_esb6300_2, 0x04, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_2, 0x08, 0x02, 0x14); - + /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x00); diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 67bd2cfb56..2549cb1327 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -55,8 +55,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -118,7 +118,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); -// mainboard_set_e7520_leds(); +// mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -128,7 +128,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c index 17ec9621ad..a3c55c1543 100644 --- a/src/mainboard/supermicro/x6dhe_g/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c @@ -31,17 +31,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ESB6300_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c +++ b/src/mainboard/supermicro/x6dhe_g/x6dhe_g_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhe_g2/debug.c b/src/mainboard/supermicro/x6dhe_g2/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhe_g2/debug.c +++ b/src/mainboard/supermicro/x6dhe_g2/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb index e621594b93..bbc4e76778 100644 --- a/src/mainboard/supermicro/x6dhe_g2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhe_g2/devicetree.cb @@ -6,12 +6,12 @@ chip northbridge/intel/e7520 # MCH device pnp 00.3 off end end device pci_domain 0 on - chip southbridge/intel/i82801ex # ICH5R + chip southbridge/intel/i82801ex # ICH5R register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" - device pci 1c.0 on - chip drivers/generic/generic + device pci 1c.0 on + chip drivers/generic/generic device pci 01.0 on end # onboard gige1 device pci 02.0 on end # onboard gige2 end @@ -25,9 +25,9 @@ chip northbridge/intel/e7520 # MCH device pci 1d.7 on end # VGA / PCI 32-bit - device pci 1e.0 on + device pci 1e.0 on chip drivers/generic/generic - device pci 01.0 on end + device pci 01.0 on end end end @@ -35,7 +35,7 @@ chip northbridge/intel/e7520 # MCH device pci 1f.0 on # ISA bridge chip superio/nsc/pc87427 device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -62,17 +62,17 @@ chip northbridge/intel/e7520 # MCH device pci 00.0 on end # Northbridge device pci 00.1 on end # Northbridge Error reporting device pci 01.0 on end - device pci 02.0 on - chip southbridge/intel/pxhd # PXHD 6700 - device pci 00.0 on end # bridge + device pci 02.0 on + chip southbridge/intel/pxhd # PXHD 6700 + device pci 00.0 on end # bridge device pci 00.1 on end # I/O apic device pci 00.2 on end # bridge device pci 00.3 on end # I/O apic end end -# device register "intrline" = "0x00070105" - device pci 04.0 on end - device pci 06.0 on end +# device register "intrline" = "0x00070105" + device pci 04.0 on end + device pci 06.0 on end end device apic_cluster 0 on diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index c50fabb0f3..81ccf85458 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v) bus_pxhd_2 = 3; } } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -162,7 +162,7 @@ static void *smp_write_config_table(void *v) bus_esb6300_2, 0x04, 0x02, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added bus_esb6300_2, 0x08, 0x02, 0x14); - + /* Standard local interrupt assignments */ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x00); diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 68ad41de40..2b0cbc84d4 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -53,8 +53,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); -// mainboard_set_e7520_leds(); +// mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) //dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -138,8 +138,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c index 17ec9621ad..a3c55c1543 100644 --- a/src/mainboard/supermicro/x6dhe_g2/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c @@ -31,17 +31,17 @@ static void disable_esb6300_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ESB6300_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ESB6300_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c b/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c +++ b/src/mainboard/supermicro/x6dhe_g2/x6dhe_g2_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhr_ig/debug.c b/src/mainboard/supermicro/x6dhr_ig/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhr_ig/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb index 921c54fff5..b989e76e8a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig/devicetree.cb @@ -1,21 +1,21 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> VGA device pci 1e.0 on end - + # -> IDE - device pci 1f.0 on + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -39,18 +39,18 @@ chip northbridge/intel/e7520 # mch register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on end - device pci 03.0 on + device pci 01.0 on end + device pci 02.0 on end + device pci 03.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 2 device pci 0.0 on end device pci 0.1 on end - device pci 0.2 on + device pci 0.2 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 02.0 on end device pci 02.1 on end end @@ -58,7 +58,7 @@ chip northbridge/intel/e7520 # mch device pci 0.3 on end end end - device pci 04.0 on + device pci 04.0 on chip southbridge/intel/pxhd # pxhd2 # Bus bridges and ioapics usually bus 5 device pci 0.0 on end diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index b98ec52479..efc7abf22a 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 7; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -159,7 +159,7 @@ static void *smp_write_config_table(void *v) } } - + /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 77c9eba0fb..16f0ac7337 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 1 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c index a4c1eec04f..44cfd10b73 100644 --- a/src/mainboard/supermicro/x6dhr_ig/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c @@ -31,17 +31,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c b/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c +++ b/src/mainboard/supermicro/x6dhr_ig/x6dhr_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } diff --git a/src/mainboard/supermicro/x6dhr_ig2/debug.c b/src/mainboard/supermicro/x6dhr_ig2/debug.c index b4f2a185b3..87c67b5964 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/debug.c +++ b/src/mainboard/supermicro/x6dhr_ig2/debug.c @@ -5,7 +5,7 @@ static void print_reg(unsigned char index) { unsigned char data; - + outb(index, 0x2e); data = inb(0x2f); print_debug("0x"); @@ -15,7 +15,7 @@ static void print_reg(unsigned char index) print_debug("\n"); return; } - + static void xbus_en(void) { /* select the XBUS function in the SIO */ @@ -25,7 +25,7 @@ static void xbus_en(void) outb(0x01, 0x2f); return; } - + static void setup_func(unsigned char func) { /* select the function in the SIO */ @@ -43,27 +43,27 @@ static void setup_func(unsigned char func) print_reg(0x75); return; } - + static void siodump(void) { int i; unsigned char data; - + print_debug("\n*** SERVER I/O REGISTERS ***\n"); for (i=0x10; i<=0x2d; i++) { print_reg((unsigned char)i); } -#if 0 +#if 0 print_debug("\n*** XBUS REGISTERS ***\n"); setup_func(0x0f); for (i=0xf0; i<=0xff; i++) { print_reg((unsigned char)i); } - + print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n"); setup_func(0x03); print_reg(0xf0); - + print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n"); setup_func(0x02); print_reg(0xf0); @@ -82,13 +82,13 @@ static void siodump(void) print_debug("\nGPDI 4: 0x"); print_debug_hex8(data); print_debug("\n"); - -#if 0 - + +#if 0 + print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n"); setup_func(0x0a); print_reg(0xf0); - + print_debug("\n*** FAN CONTROL REGISTERS ***\n"); setup_func(0x09); print_reg(0xf0); @@ -103,11 +103,11 @@ static void siodump(void) print_reg(0xf7); print_reg(0xfe); print_reg(0xff); - + print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n"); setup_func(0x14); print_reg(0xf0); -#endif +#endif return; } @@ -124,8 +124,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -144,7 +144,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -164,19 +164,19 @@ static void dump_bar14(unsigned dev) { int i; unsigned long bar; - + print_debug("BAR 14 Dump\n"); - + bar = pci_read_config32(dev, 0x14); for(i = 0; i <= 0x300; i+=4) { -#if 0 +#if 0 unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); print_debug_char(':'); } val = pci_read_config8(dev, i); -#endif +#endif if((i%4)==0) { print_debug("\n"); print_debug_hex16(i); @@ -191,8 +191,8 @@ static void dump_bar14(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); + for(dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { uint32_t id; id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -215,8 +215,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -241,8 +241,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -278,7 +278,7 @@ void dump_spd_registers(void) print_debug("\n"); print_debug("dimm "); print_debug_hex8(device); - + for(i = 0; (i < 256) ; i++) { unsigned char byte; if ((i % 16) == 0) { @@ -291,7 +291,7 @@ void dump_spd_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -311,7 +311,7 @@ void dump_ipmi_registers(void) print_debug("\n"); print_debug("ipmi "); print_debug_hex8(device); - + for(i = 0; (i < 8) ; i++) { unsigned char byte; status = smbus_read_byte(device, 2); @@ -319,7 +319,7 @@ void dump_ipmi_registers(void) print_debug("bad device: "); print_debug_hex8(-status); print_debug("\n"); - break; + break; } print_debug_hex8(status); print_debug_char(' '); @@ -327,4 +327,4 @@ void dump_ipmi_registers(void) device += SMBUS_MEM_DEVICE_INC; print_debug("\n"); } -} +} diff --git a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb index 318d492b9f..ed3fa65219 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb +++ b/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb @@ -1,21 +1,21 @@ chip northbridge/intel/e7520 # mch - device pci_domain 0 on + device pci_domain 0 on chip southbridge/intel/i82801ex # i82801er # USB ports device pci 1d.0 on end device pci 1d.1 on end - device pci 1d.2 on end + device pci 1d.2 on end device pci 1d.3 on end device pci 1d.7 on end - + # -> Bridge device pci 1e.0 on end - + # -> ISA - device pci 1f.0 on + device pci 1f.0 on chip superio/winbond/w83627hf device pnp 2e.0 off end - device pnp 2e.2 on + device pnp 2e.2 on io 0x60 = 0x3f8 irq 0x70 = 4 end @@ -34,22 +34,22 @@ chip northbridge/intel/e7520 # mch end # -> IDE device pci 1f.1 on end - # -> SATA + # -> SATA device pci 1f.2 on end device pci 1f.3 on end register "pirq_a_d" = "0x0b070a05" register "pirq_e_h" = "0x0a808080" end - device pci 00.0 on end + device pci 00.0 on end device pci 00.1 on end - device pci 01.0 on end - device pci 02.0 on + device pci 01.0 on end + device pci 02.0 on chip southbridge/intel/pxhd # pxhd1 # Bus bridges and ioapics usually bus 1 - device pci 0.0 on + device pci 0.0 on # On board gig e1000 - chip drivers/generic/generic + chip drivers/generic/generic device pci 03.0 on end device pci 03.1 on end end diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index 78a863c7a1..3e95e108d1 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) mc->reserved = 0; smp_write_processors(mc); - + { device_t dev; @@ -98,9 +98,9 @@ static void *smp_write_config_table(void *v) bus_pxhd_4 = 6; } - + } - + /* define bus and isa numbers */ for(bus_num = 0; bus_num < bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); @@ -135,7 +135,7 @@ static void *smp_write_config_table(void *v) else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); } - } + } /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index d2b845eac6..8f5ca7930e 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -54,8 +54,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void main(unsigned long bist) { /* - * - * + * + * */ static const struct mem_controller mch[] = { { @@ -117,7 +117,7 @@ static void main(unsigned long bist) #endif disable_watchdogs(); // dump_ipmi_registers(); - mainboard_set_e7520_leds(); + mainboard_set_e7520_leds(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); @@ -127,7 +127,7 @@ static void main(unsigned long bist) dump_bar14(PCI_DEV(0, 0x00, 0)); #endif -#if 0 // temporarily disabled +#if 0 // temporarily disabled /* Check the first 1M */ // ram_check(0x00000000, 0x000100000); // ram_check(0x00000000, 0x000a0000); @@ -139,8 +139,8 @@ static void main(unsigned long bist) #if 0 ram_check(0x00000000, 0x02000000); #endif - -#if 0 + +#if 0 while(1) { hlt(); } diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c index a4c1eec04f..44cfd10b73 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c @@ -31,17 +31,17 @@ static void disable_ich5_watchdog(void) value = pci_read_config16(dev, 0x04); value |= (1 << 10); pci_write_config16(dev, 0x04, value); - + /* Set and enable acpibase */ pci_write_config32(dev, 0x40, ICH5_WDBASE | 1); pci_write_config8(dev, 0x44, 0x10); base = ICH5_WDBASE + 0x60; - + /* Set bit 11 in TCO1_CNT */ value = inw(base + 0x08); value |= 1 << 11; outw(value, base + 0x08); - + /* Clear TCO timeout status */ outw(0x0008, base + 0x04); outw(0x0002, base + 0x06); @@ -86,7 +86,7 @@ static void disable_jarell_frb3(void) outl(value, base + 0x38); value &= ~(1 << 16); outl(value, base + 0x38); -#endif +#endif } static void disable_watchdogs(void) diff --git a/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c b/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c index 82c070b0c1..cc3e41eb9f 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c +++ b/src/mainboard/supermicro/x6dhr_ig2/x6dhr2_fixups.c @@ -9,13 +9,13 @@ static void mch_reset(void) static void mainboard_set_e7520_pll(unsigned bits) { - return; + return; } static void mainboard_set_e7520_leds(void) { - return; + return; } |