Leverage the Pstate table created by AGESA.

The name of processor created by AGESA is P00n, whose P is
BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts
from 0. The dsdt should be aligned with that.
This feature has only been tested on persimmon. The changes on all the
other boards were propagated.

Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/884
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

3 files changed, 61 insertions, 137 deletions

diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
deleted file mode 100644
index 5eca9cc5c7..0000000000
--- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/* This file defines the processor and performance state capability
- * for each core in the system.  It is included into the DSDT for each
- * core.  It assumes that each core of the system has the same performance
- * characteristics.
-*/
-/*
-DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
-	{
-		Scope (\_PR) {
-		Processor(CPU0,0,0x808,0x06) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU1,1,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU2,2,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-		Processor(CPU3,3,0x0,0x0) {
-			#include "cpstate.asl"
-		}
-	}
-*/
-	/* P-state support: The maximum number of P-states supported by the */
-	/* CPUs we'll use is 6. */
-	/* Get from AMI BIOS. */
-	Name(_PSS, Package(){
-		Package ()
-		{
-		    0x00000AF0,
-		    0x0000BF81,
-		    0x00000002,
-		    0x00000002,
-		    0x00000000,
-		    0x00000000
-		},
-
-		Package ()
-		{
-		    0x00000578,
-		    0x000076F2,
-		    0x00000002,
-		    0x00000002,
-		    0x00000001,
-		    0x00000001
-		}
-	})
-
-	Name(_PCT, Package(){
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
-		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
-	})
-
-	Method(_PPC, 0){
-		Return(0)
-	}
diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c
index ac9acd6559..77c0772c22 100644
--- a/src/mainboard/supermicro/h8qgi/acpi_tables.c
+++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c
@@ -297,7 +297,8 @@ unsigned long write_acpi_tables(unsigned long start)
 		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
 	}
 
-#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	/* The DSDT needs additional work for the AGESA SSDT Pstate table */
+	/* Keep the comment for a while. */
 	current = (current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
@@ -305,11 +306,10 @@ unsigned long write_acpi_tables(unsigned long start)
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
+		acpi_add_table(rsdp,ssdt);
 	} else {
-		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
+		printk(BIOS_DEBUG, "  AGESA SSDT Pstate table NULL. Skipping.\n");
 	}
-	acpi_add_table(rsdp,ssdt);
-#endif
 
 	current = (current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl
index 137a90d064..2955eeacff 100644
--- a/src/mainboard/supermicro/h8qgi/dsdt.asl
+++ b/src/mainboard/supermicro/h8qgi/dsdt.asl
@@ -65,69 +65,68 @@ DefinitionBlock (
 	 */
 	Scope (\_PR) {		/* define processor scope */
 		Processor(
-			P000,		/* name space name */
+			C000,		/* name space name, align with BLDCFG_PROCESSOR_SCOPE_NAME[01] */
 			0x00,		/* Unique number for this processor */
 			0x810,		/* PBLK system I/O address !hardcoded! */
 			0x06		/* PBLKLEN for boot processor */
 			) {
-			//#include "acpi/cpstate.asl"
 		}
-		Processor(P001, 0x01, 0x00000000, 0x00) {}
-		Processor(P002, 0x02, 0x00000000, 0x00) {}
-		Processor(P003, 0x03, 0x00000000, 0x00) {}
-		Processor(P004, 0x04, 0x00000000, 0x00) {}
-		Processor(P005, 0x05, 0x00000000, 0x00) {}
-		Processor(P006, 0x06, 0x00000000, 0x00) {}
-		Processor(P007, 0x07, 0x00000000, 0x00) {}
-		Processor(P008, 0x08, 0x00000000, 0x00) {}
-		Processor(P009, 0x09, 0x00000000, 0x00) {}
-		Processor(P00A, 0x0A, 0x00000000, 0x00) {}
-		Processor(P00B, 0x0B, 0x00000000, 0x00) {}
-		Processor(P00C, 0x0C, 0x00000000, 0x00) {}
-		Processor(P00D, 0x0D, 0x00000000, 0x00) {}
-		Processor(P00E, 0x0E, 0x00000000, 0x00) {}
-		Processor(P00F, 0x0F, 0x00000000, 0x00) {}
-		Processor(P010, 0x10, 0x00000000, 0x00) {}
-		Processor(P011, 0x11, 0x00000000, 0x00) {}
-		Processor(P012, 0x12, 0x00000000, 0x00) {}
-		Processor(P013, 0x13, 0x00000000, 0x00) {}
-		Processor(P014, 0x14, 0x00000000, 0x00) {}
-		Processor(P015, 0x15, 0x00000000, 0x00) {}
-		Processor(P016, 0x16, 0x00000000, 0x00) {}
-		Processor(P017, 0x17, 0x00000000, 0x00) {}
-		Processor(P018, 0x18, 0x00000000, 0x00) {}
-		Processor(P019, 0x19, 0x00000000, 0x00) {}
-		Processor(P01A, 0x1A, 0x00000000, 0x00) {}
-		Processor(P01B, 0x1B, 0x00000000, 0x00) {}
-		Processor(P01C, 0x1C, 0x00000000, 0x00) {}
-		Processor(P01D, 0x1D, 0x00000000, 0x00) {}
-		Processor(P01E, 0x1E, 0x00000000, 0x00) {}
-		Processor(P01F, 0x1F, 0x00000000, 0x00) {}
-		Processor(P020, 0x20, 0x00000000, 0x00) {}
-		Processor(P021, 0x21, 0x00000000, 0x00) {}
-		Processor(P022, 0x22, 0x00000000, 0x00) {}
-		Processor(P023, 0x23, 0x00000000, 0x00) {}
-		Processor(P024, 0x24, 0x00000000, 0x00) {}
-		Processor(P025, 0x25, 0x00000000, 0x00) {}
-		Processor(P026, 0x26, 0x00000000, 0x00) {}
-		Processor(P027, 0x27, 0x00000000, 0x00) {}
-		Processor(P028, 0x28, 0x00000000, 0x00) {}
-		Processor(P029, 0x29, 0x00000000, 0x00) {}
-		Processor(P02A, 0x2A, 0x00000000, 0x00) {}
-		Processor(P02B, 0x2B, 0x00000000, 0x00) {}
-		Processor(P02C, 0x2C, 0x00000000, 0x00) {}
-		Processor(P02D, 0x2D, 0x00000000, 0x00) {}
-		Processor(P02E, 0x2E, 0x00000000, 0x00) {}
-		Processor(P02F, 0x2F, 0x00000000, 0x00) {}
-		Alias (P000, CPU0)
-		Alias (P001, CPU1)
-		Alias (P002, CPU2)
-		Alias (P003, CPU3)
-		Alias (P004, CPU4)
-		Alias (P005, CPU5)
-		Alias (P006, CPU6)
-		Alias (P007, CPU7)
-		Alias (P008, CPU8)
+		Processor(C001, 0x01, 0x00000000, 0x00) {}
+		Processor(C002, 0x02, 0x00000000, 0x00) {}
+		Processor(C003, 0x03, 0x00000000, 0x00) {}
+		Processor(C004, 0x04, 0x00000000, 0x00) {}
+		Processor(C005, 0x05, 0x00000000, 0x00) {}
+		Processor(C006, 0x06, 0x00000000, 0x00) {}
+		Processor(C007, 0x07, 0x00000000, 0x00) {}
+		Processor(C008, 0x08, 0x00000000, 0x00) {}
+		Processor(C009, 0x09, 0x00000000, 0x00) {}
+		Processor(C00A, 0x0A, 0x00000000, 0x00) {}
+		Processor(C00B, 0x0B, 0x00000000, 0x00) {}
+		Processor(C00C, 0x0C, 0x00000000, 0x00) {}
+		Processor(C00D, 0x0D, 0x00000000, 0x00) {}
+		Processor(C00E, 0x0E, 0x00000000, 0x00) {}
+		Processor(C00F, 0x0F, 0x00000000, 0x00) {}
+		Processor(C010, 0x10, 0x00000000, 0x00) {}
+		Processor(C011, 0x11, 0x00000000, 0x00) {}
+		Processor(C012, 0x12, 0x00000000, 0x00) {}
+		Processor(C013, 0x13, 0x00000000, 0x00) {}
+		Processor(C014, 0x14, 0x00000000, 0x00) {}
+		Processor(C015, 0x15, 0x00000000, 0x00) {}
+		Processor(C016, 0x16, 0x00000000, 0x00) {}
+		Processor(C017, 0x17, 0x00000000, 0x00) {}
+		Processor(C018, 0x18, 0x00000000, 0x00) {}
+		Processor(C019, 0x19, 0x00000000, 0x00) {}
+		Processor(C01A, 0x1A, 0x00000000, 0x00) {}
+		Processor(C01B, 0x1B, 0x00000000, 0x00) {}
+		Processor(C01C, 0x1C, 0x00000000, 0x00) {}
+		Processor(C01D, 0x1D, 0x00000000, 0x00) {}
+		Processor(C01E, 0x1E, 0x00000000, 0x00) {}
+		Processor(C01F, 0x1F, 0x00000000, 0x00) {}
+		Processor(C020, 0x20, 0x00000000, 0x00) {}
+		Processor(C021, 0x21, 0x00000000, 0x00) {}
+		Processor(C022, 0x22, 0x00000000, 0x00) {}
+		Processor(C023, 0x23, 0x00000000, 0x00) {}
+		Processor(C024, 0x24, 0x00000000, 0x00) {}
+		Processor(C025, 0x25, 0x00000000, 0x00) {}
+		Processor(C026, 0x26, 0x00000000, 0x00) {}
+		Processor(C027, 0x27, 0x00000000, 0x00) {}
+		Processor(C028, 0x28, 0x00000000, 0x00) {}
+		Processor(C029, 0x29, 0x00000000, 0x00) {}
+		Processor(C02A, 0x2A, 0x00000000, 0x00) {}
+		Processor(C02B, 0x2B, 0x00000000, 0x00) {}
+		Processor(C02C, 0x2C, 0x00000000, 0x00) {}
+		Processor(C02D, 0x2D, 0x00000000, 0x00) {}
+		Processor(C02E, 0x2E, 0x00000000, 0x00) {}
+		Processor(C02F, 0x2F, 0x00000000, 0x00) {}
+		Alias (C000, CPU0)
+		Alias (C001, CPU1)
+		Alias (C002, CPU2)
+		Alias (C003, CPU3)
+		Alias (C004, CPU4)
+		Alias (C005, CPU5)
+		Alias (C006, CPU6)
+		Alias (C007, CPU7)
+		Alias (C008, CPU8)
 	} /* End _PR scope */
 
 	/* PIC IRQ mapping registers, C00h-C01h */