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authorMichael Niewöhner <foss@mniewoehner.de>2020-11-08 19:32:13 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-12-10 02:26:22 +0000
commitf105c4164ed9f814ef2325e9e4500c3e5723355f (patch)
tree2fd00ff996ca202b1bd21c40423a7df06d9e8824 /src/mainboard/supermicro
parent7f623f8e466f2eb45d9b571f7e752f42eee5c3db (diff)
downloadcoreboot-f105c4164ed9f814ef2325e9e4500c3e5723355f.tar.xz
mb/supermicro/x11ssm-f: (re)configure unconnected pads
Correct unconnected pads that are configured different currently by copying vendor configuration while porting the board. Add internal pull resistors to all unconnected pads, that do not have an external pull resistor, to prevent floating. The pads have been determined by dissecting a dead board. This commit only changes pads, that are not connected at all and don't have any via, so we can be absolutely sure there is no other connection. Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c162
1 files changed, 81 insertions, 81 deletions
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c
index 0b658acbf8..9294a0f145 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c
@@ -19,41 +19,41 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),
PAD_NC(GPP_A12, NONE),
- PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ PAD_NC(GPP_A13, UP_20K),
+ PAD_NC(GPP_A14, UP_20K),
+ PAD_NC(GPP_A15, UP_20K),
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
- PAD_NC(GPP_A17, NONE),
+ PAD_NC(GPP_A17, UP_20K),
PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF),
/* GPP_A19 - RESERVED */
- PAD_NC(GPP_A20, NONE),
- PAD_NC(GPP_A21, NONE),
- PAD_NC(GPP_A22, NONE),
- PAD_NC(GPP_A23, NONE),
+ PAD_NC(GPP_A20, UP_20K),
+ PAD_NC(GPP_A21, UP_20K),
+ PAD_NC(GPP_A22, UP_20K),
+ PAD_NC(GPP_A23, UP_20K),
/* GPIO Group GPP_B */
PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE),
PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE),
PAD_NC(GPP_B2, NONE),
- PAD_NC(GPP_B3, NONE),
- PAD_NC(GPP_B4, NONE),
- PAD_NC(GPP_B5, NONE),
- PAD_NC(GPP_B6, NONE),
- PAD_NC(GPP_B7, NONE),
- PAD_NC(GPP_B8, NONE),
- PAD_NC(GPP_B9, NONE),
- PAD_NC(GPP_B10, NONE),
+ PAD_NC(GPP_B3, UP_20K),
+ PAD_NC(GPP_B4, UP_20K),
+ PAD_NC(GPP_B5, UP_20K),
+ PAD_NC(GPP_B6, UP_20K),
+ PAD_NC(GPP_B7, UP_20K),
+ PAD_NC(GPP_B8, UP_20K),
+ PAD_NC(GPP_B9, UP_20K),
+ PAD_NC(GPP_B10, UP_20K),
PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR + JBR1 ("Top-Block Swap") */
- PAD_NC(GPP_B15, NONE),
- PAD_NC(GPP_B16, NONE),
- PAD_NC(GPP_B17, NONE),
+ PAD_NC(GPP_B15, UP_20K),
+ PAD_NC(GPP_B16, UP_20K),
+ PAD_NC(GPP_B17, UP_20K),
PAD_NC(GPP_B18, NONE),
- PAD_NC(GPP_B19, NONE),
+ PAD_NC(GPP_B19, UP_20K),
PAD_CFG_GPO(GPP_B20, 0, PLTRST), /* BMC POST_COMPLETE */
- PAD_NC(GPP_B21, NONE),
+ PAD_NC(GPP_B21, UP_20K),
PAD_NC(GPP_B22, NONE),
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
@@ -70,9 +70,9 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF),
PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF),
PAD_NC(GPP_C11, NONE),
- PAD_NC(GPP_C12, NONE),
- PAD_NC(GPP_C13, NONE),
- PAD_NC(GPP_C14, NONE),
+ PAD_NC(GPP_C12, UP_20K),
+ PAD_NC(GPP_C13, UP_20K),
+ PAD_NC(GPP_C14, UP_20K),
PAD_NC(GPP_C15, NONE),
PAD_NC(GPP_C16, NONE),
PAD_NC(GPP_C17, NONE),
@@ -87,37 +87,37 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_D0, NONE),
PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), /* Power LEDs onboard + JF1 */
PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, INVERT), /* BMC NMI# */
- PAD_NC(GPP_D3, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE),
- PAD_NC(GPP_D5, NONE),
- PAD_NC(GPP_D6, NONE),
- PAD_NC(GPP_D7, NONE),
- PAD_NC(GPP_D8, NONE),
+ PAD_NC(GPP_D3, DN_20K),
+ PAD_NC(GPP_D4, UP_20K),
+ PAD_NC(GPP_D5, UP_20K),
+ PAD_NC(GPP_D6, UP_20K),
+ PAD_NC(GPP_D7, UP_20K),
+ PAD_NC(GPP_D8, UP_20K),
PAD_NC(GPP_D9, NONE),
- PAD_NC(GPP_D10, NONE),
- PAD_NC(GPP_D11, NONE),
- PAD_NC(GPP_D12, NONE),
- PAD_NC(GPP_D13, NONE),
+ PAD_NC(GPP_D10, UP_20K),
+ PAD_NC(GPP_D11, UP_20K),
+ PAD_NC(GPP_D12, UP_20K),
+ PAD_NC(GPP_D13, UP_20K),
PAD_NC(GPP_D14, NONE),
- PAD_NC(GPP_D15, NONE),
- PAD_NC(GPP_D16, NONE),
- PAD_NC(GPP_D17, NONE),
+ PAD_NC(GPP_D15, UP_20K),
+ PAD_NC(GPP_D16, UP_20K),
+ PAD_NC(GPP_D17, UP_20K),
PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), /* PERST# CPU PCIe Slots */
PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), /* PERST# PCH PCIe Slots */
- PAD_NC(GPP_D20, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE),
+ PAD_NC(GPP_D20, UP_20K),
+ PAD_NC(GPP_D21, UP_20K),
PAD_CFG_GPI(GPP_D22, NONE, RSMRST), /* BMC enable/disable jumper JPB1 */
- PAD_NC(GPP_D23, NONE),
+ PAD_NC(GPP_D23, UP_20K),
/* GPIO Group GPP_E */
- PAD_NC(GPP_E0, NONE),
- PAD_NC(GPP_E1, NONE),
- PAD_NC(GPP_E2, NONE),
+ PAD_NC(GPP_E0, UP_20K),
+ PAD_NC(GPP_E1, UP_20K),
+ PAD_NC(GPP_E2, UP_20K),
PAD_NC(GPP_E3, NONE),
- PAD_NC(GPP_E4, NONE),
- PAD_NC(GPP_E5, NONE),
+ PAD_NC(GPP_E4, UP_20K),
+ PAD_NC(GPP_E5, UP_20K),
PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, INVERT), /* NMI# (BMC WDT + JF1) */
- PAD_NC(GPP_E7, NONE),
+ PAD_NC(GPP_E7, UP_20K),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
@@ -125,29 +125,29 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* GPIO Group GPP_F */
- PAD_NC(GPP_F0, NONE),
- PAD_NC(GPP_F1, NONE),
- PAD_NC(GPP_F2, NONE),
- PAD_NC(GPP_F3, NONE),
- PAD_NC(GPP_F4, NONE),
+ PAD_NC(GPP_F0, UP_20K),
+ PAD_NC(GPP_F1, UP_20K),
+ PAD_NC(GPP_F2, UP_20K),
+ PAD_NC(GPP_F3, UP_20K),
+ PAD_NC(GPP_F4, UP_20K),
PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE),
- PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF),
+ PAD_NC(GPP_F6, UP_20K),
+ PAD_NC(GPP_F7, UP_20K),
+ PAD_NC(GPP_F8, UP_20K),
+ PAD_NC(GPP_F9, UP_20K),
PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
- PAD_NC(GPP_F14, NONE),
+ PAD_NC(GPP_F14, UP_20K),
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
PAD_NC(GPP_F17, NONE),
PAD_NC(GPP_F18, NONE),
- PAD_NC(GPP_F19, NONE),
- PAD_NC(GPP_F20, NONE),
- PAD_NC(GPP_F21, NONE),
- PAD_NC(GPP_F22, NONE),
+ PAD_NC(GPP_F19, UP_20K),
+ PAD_NC(GPP_F20, UP_20K),
+ PAD_NC(GPP_F21, UP_20K),
+ PAD_NC(GPP_F22, UP_20K),
PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE),
/* GPIO Group GPP_G */
@@ -155,14 +155,14 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_G1, NONE), /* JPCIE6-B32 (DGPU_PWR_OK) */
PAD_NC(GPP_G2, NONE), /* JPCIE6-B30 (DGPU_SEL#) */
PAD_NC(GPP_G3, NONE), /* JPCIE6-B82 (DGPU_PRSNT#) */
- PAD_NC(GPP_G4, NONE),
- PAD_NC(GPP_G5, NONE),
- PAD_NC(GPP_G6, NONE),
- PAD_NC(GPP_G7, NONE),
+ PAD_NC(GPP_G4, UP_20K),
+ PAD_NC(GPP_G5, UP_20K),
+ PAD_NC(GPP_G6, UP_20K),
+ PAD_NC(GPP_G7, UP_20K),
PAD_NC(GPP_G8, NONE),
- PAD_NC(GPP_G9, NONE),
- PAD_NC(GPP_G10, NONE),
- PAD_NC(GPP_G11, NONE),
+ PAD_NC(GPP_G9, UP_20K),
+ PAD_NC(GPP_G10, UP_20K),
+ PAD_NC(GPP_G11, UP_20K),
PAD_CFG_GPI(GPP_G12, NONE, PLTRST), /* SKU_ID[0] */
PAD_CFG_GPI(GPP_G13, NONE, PLTRST), /* SKU_ID[1] */
PAD_CFG_GPI(GPP_G14, NONE, PLTRST), /* SKU_ID[2] */
@@ -172,15 +172,15 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* BMC NMI# */
PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), /* BMC SMI# */
PAD_CFG_GPI(GPP_G20, NONE, PLTRST), /* JPI2C1 PWRFAIL# */
- PAD_NC(GPP_G21, NONE),
+ PAD_NC(GPP_G21, UP_20K),
PAD_NC(GPP_G22, NONE),
PAD_NC(GPP_G23, NONE),
/* GPIO Group GPP_H */
PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE),
PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE),
+ PAD_NC(GPP_H2, UP_20K),
+ PAD_NC(GPP_H3, UP_20K),
PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE),
@@ -189,17 +189,17 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE),
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
- PAD_NC(GPP_H12, NONE),
- PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+ PAD_NC(GPP_H12, UP_20K),
+ PAD_NC(GPP_H13, NONE),
PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
PAD_NC(GPP_H15, NONE),
- PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
- PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+ PAD_NC(GPP_H16, NONE),
+ PAD_NC(GPP_H17, NONE),
PAD_NC(GPP_H18, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE),
- PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE),
+ PAD_NC(GPP_H19, UP_20K),
+ PAD_NC(GPP_H20, UP_20K),
+ PAD_NC(GPP_H21, UP_20K),
+ PAD_NC(GPP_H22, UP_20K),
PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE),
/* GPIO Group GPP_I */
@@ -223,10 +223,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
- PAD_NC(GPD7, NONE),
+ PAD_NC(GPD7, UP_20K),
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
- PAD_NC(GPD9, NONE),
- PAD_NC(GPD10, NONE),
+ PAD_NC(GPD9, UP_20K),
+ PAD_NC(GPD10, UP_20K),
PAD_NC(GPD11, NONE),
};