mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol references

Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

10 files changed, 25 insertions, 25 deletions

diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index d0ab05e027..f173d1a719 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -154,13 +154,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
 	set_sysinfo_in_ram(0);	// in BSP so could hold all ap until sysinfo is in ram
-#if CONFIG_DEBUG_SMBUS
+#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
 	dump_smbus_registers();
 #endif
 	setup_coherent_ht_domain();	// routing table and start other core0
 
 	wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	// It is said that we should start core1 after all core0 launched
 	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 	 * So here need to make sure last core0 is started, esp for two way system,
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it will set up chains and store link pair for optimization later */
 	ht_setup_chains_x(sysinfo);	// it will init sblnk and sbbusn, nodes, sbdn
 
-#if CONFIG_SET_FIDVID
+#if IS_ENABLED(CONFIG_SET_FIDVID)
 	{
 		msr_t msr;
 		msr = rdmsr(0xc0010042);
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index e4ee1c842d..3f01c92ca5 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_coherent_ht_domain(); // routing table and start other core0
 
 	wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	// It is said that we should start core1 after all core0 launched
 	/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 	 * So here need to make sure last core0 is started, esp for two way system,
@@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* it will set up chains and store link pair for optimization later */
 	ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 
-#if CONFIG_SET_FIDVID
+#if IS_ENABLED(CONFIG_SET_FIDVID)
 	{
 		msr_t msr;
 		msr = rdmsr(0xc0010042);
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index d457f1bd91..e100876d5a 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 
 	wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores(bsp_apicid);
@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x38);
 
-#if CONFIG_SET_FIDVID
+#if IS_ENABLED(CONFIG_SET_FIDVID)
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
 		msr.hi, msr.lo);
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index 4db2c6f53c..b146afe0d6 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -426,10 +426,10 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
  */
 
 /*
-#if CONFIG_CPU_AMD_AGESA_FAMILY15
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
   #define BLDOPT_REMOVE_FAMILY_10_SUPPORT         TRUE
 #endif
-#if CONFIG_CPU_AMD_AGESA_FAMILY10
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
   #define BLDOPT_REMOVE_FAMILY_15_SUPPORT         TRUE
 #endif
 */
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
index 35ddfbb5b5..6607094281 100644
--- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
@@ -27,10 +27,10 @@
  * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
  */
 #ifndef DEFAULT_HT_PATH
-#if CONFIG_CPU_AMD_AGESA_FAMILY10
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
 #define DEFAULT_HT_PATH		{0x0, 0x3}
 #endif
-#if CONFIG_CPU_AMD_AGESA_FAMILY15
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
 #define DEFAULT_HT_PATH		{0x0, 0x1}
 #endif
 #endif
diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
index a5f371dbf1..62b618f70a 100644
--- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h
+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
@@ -36,13 +36,13 @@
  * before AGESA module get call.
  */
 #ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024
+#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
 #define BIOS_SIZE BIOS_SIZE_1M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
 #define BIOS_SIZE BIOS_SIZE_2M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
 #define BIOS_SIZE BIOS_SIZE_4M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
 #define BIOS_SIZE BIOS_SIZE_8M
 #endif
 #endif
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 26f3da710a..3554a05fce 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -239,7 +239,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	*/
 
 	wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores(bsp_apicid);
@@ -249,7 +249,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x38);
 
-#if CONFIG_SET_FIDVID
+#if IS_ENABLED(CONFIG_SET_FIDVID)
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h
index 35ddfbb5b5..6607094281 100644
--- a/src/mainboard/supermicro/h8scm/rd890_cfg.h
+++ b/src/mainboard/supermicro/h8scm/rd890_cfg.h
@@ -27,10 +27,10 @@
  * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
  */
 #ifndef DEFAULT_HT_PATH
-#if CONFIG_CPU_AMD_AGESA_FAMILY10
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
 #define DEFAULT_HT_PATH		{0x0, 0x3}
 #endif
-#if CONFIG_CPU_AMD_AGESA_FAMILY15
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
 #define DEFAULT_HT_PATH		{0x0, 0x1}
 #endif
 #endif
diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h
index c067095d3e..62b618f70a 100644
--- a/src/mainboard/supermicro/h8scm/sb700_cfg.h
+++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h
@@ -36,13 +36,13 @@
  * before AGESA module get call.
  */
 #ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
 #define BIOS_SIZE BIOS_SIZE_1M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
 #define BIOS_SIZE BIOS_SIZE_2M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
 #define BIOS_SIZE BIOS_SIZE_4M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
 #define BIOS_SIZE BIOS_SIZE_8M
 #endif
 #endif
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 091514d91a..60288e0329 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
-#if CONFIG_LOGICAL_CPUS
+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores(bsp_apicid);
@@ -167,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sr5650_early_setup();
 	sb7xx_51xx_early_setup();
 
-#if CONFIG_SET_FIDVID
+#if IS_ENABLED(CONFIG_SET_FIDVID)
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);