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| author | Keith Hui <buurin@gmail.com> | 2017-09-11 18:41:16 -0400 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-12 07:54:59 +0000 |
| commit | 0a9982f3fb7d20325b437656205f450505967a3d (patch) | |
| tree | e9f94fb190b6c45a6efe6522e3de672c3a807ec3 /src/mainboard/supermicro | |
| parent | 5036ebd190e04ff9bbb69dde3d0524206c328601 (diff) | |
| download | coreboot-0a9982f3fb7d20325b437656205f450505967a3d.tar.xz | |
cpu/intel/car/cache_as_ram.inc: Fix long standing issues
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE
and CONFIG_DCACHE_RAM_SIZE for consistency.
Do not set %ebp before and switch directly to stack returned by
romstage_main().
Remove an unneeded 4-byte gap in CAR stack.
The caching strategy for flash XIP area should be WRPROT.
Clarify the various comments in the file on the logic.
Together they lay the groundwork for bringing EARLY_CBMEM_INIT to
intel/slot_1 boards.
Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21503
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/supermicro')
0 files changed, 0 insertions, 0 deletions