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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-04-29 13:09:50 +1000
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-31 21:17:37 +0200
commitbeb0f2631fe6e49e86687cc3a7cf63ce41157a45 (patch)
treeefafc117389de92204dcbc98e6edd9ad56c2212c /src/mainboard/supermicro
parent9068788a8f0c96a5153fcd4e5ed80eac80b060c6 (diff)
downloadcoreboot-beb0f2631fe6e49e86687cc3a7cf63ce41157a45.tar.xz
superio/winbond/w83627hf: Avoid .c includes in mainboards
Move towards the removal of the superio model specific xxx_serial_enable implementation. Make remaining superio romstage parts link-time symbols and fix corresponding mainboards to match. The following mainboards remain unconverted as they are ROMCC: - mainboard/supermicro/x6dai_g - mainboard/supermicro/x6dhe_g - mainboard/supermicro/x6dhr_ig - mainboard/supermicro/x6dhr_ig2 and so block the final removal of w83627hf_serial_enable(). Special cases: - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func Provide local superio pnp_ programming entry/exit functions as to avoid making superio implementation global symbols. Although this is not the proper/final solution, it does mitigate possible symbol collisions and allow for continued superio refactorisation. Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5601 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8dme/romstage.c6
-rw-r--r--src/mainboard/supermicro/h8dmr/romstage.c8
-rw-r--r--src/mainboard/supermicro/h8dmr_fam10/romstage.c6
-rw-r--r--src/mainboard/supermicro/h8qme_fam10/romstage.c22
-rw-r--r--src/mainboard/supermicro/x6dai_g/romstage.c2
-rw-r--r--src/mainboard/supermicro/x6dhe_g/romstage.c2
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/romstage.c2
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/romstage.c2
8 files changed, 32 insertions, 18 deletions
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index df5e2c8e7e..47f5806c67 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -33,8 +33,8 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/early_serial.c"
-#include "superio/winbond/w83627hf/early_init.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
w83627hf_set_clksel_48(DUMMY_DEV);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 8ed7e6de69..7d1f834a7c 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -36,8 +36,8 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/early_serial.c"
-#include "superio/winbond/w83627hf/early_init.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -114,8 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- w83627hf_set_clksel_48(DUMMY_DEV);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ w83627hf_set_clksel_48(DUMMY_DEV);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 3f6ea70609..cd185f3c39 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -39,8 +39,8 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627hf/early_serial.c"
-#include "superio/winbond/w83627hf/early_init.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -122,7 +122,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32);
w83627hf_set_clksel_48(DUMMY_DEV);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index cca464c1f0..9898a25c0f 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -39,8 +39,8 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdfam10/reset_test.c"
-#include "superio/winbond/w83627hf/early_serial.c"
-#include "superio/winbond/w83627hf/early_init.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -114,6 +114,20 @@ static const u8 spd_addr[] = {
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
+/* TODO: superio code should really not be in mainboard */
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0x87, port);
+ outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+ u16 port = dev >> 8;
+ outb(0xaa, port);
+}
+
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
@@ -172,8 +186,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x32);
- w83627hf_set_clksel_48(DUMMY_DEV);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ w83627hf_set_clksel_48(DUMMY_DEV);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
write_GPIO();
diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c
index f57adafe02..c998466c39 100644
--- a/src/mainboard/supermicro/x6dai_g/romstage.c
+++ b/src/mainboard/supermicro/x6dai_g/romstage.c
@@ -9,13 +9,13 @@
#include "lib/delay.c"
#include "southbridge/intel/esb6300/early_smbus.c"
#include "northbridge/intel/e7525/raminit.h"
-#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
#include "southbridge/intel/esb6300/reset.c"
#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/e7525/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c
index 071bb35036..b1c3cfa998 100644
--- a/src/mainboard/supermicro/x6dhe_g/romstage.c
+++ b/src/mainboard/supermicro/x6dhe_g/romstage.c
@@ -9,13 +9,13 @@
#include "lib/delay.c"
#include "southbridge/intel/esb6300/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
-#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
#include "southbridge/intel/esb6300/reset.c"
#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c
index 9c61d60642..2dc96c1705 100644
--- a/src/mainboard/supermicro/x6dhr_ig/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c
@@ -7,13 +7,13 @@
#include <console/console.h>
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
-#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
#include "southbridge/intel/i82801ex/reset.c"
#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>
diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
index 4690a0c2fc..0f2a644ba2 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c
@@ -7,13 +7,13 @@
#include <console/console.h>
#include "southbridge/intel/i82801ex/early_smbus.c"
#include "northbridge/intel/e7520/raminit.h"
-#include "superio/winbond/w83627hf/w83627hf.h"
#include "cpu/x86/lapic/boot_cpu.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "debug.c"
#include "watchdog.c"
#include "southbridge/intel/i82801ex/reset.c"
#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "northbridge/intel/e7520/memory_initialized.c"
#include "cpu/x86/bist.h"
#include <spd.h>