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authorStefan Reinauer <stepan@coresystems.de>2009-06-30 15:17:49 +0000
committerStefan Reinauer <stepan@openbios.org>2009-06-30 15:17:49 +0000
commit0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch)
tree81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/mainboard/supermicro
parent9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff)
downloadcoreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/h8dme/Config.lb46
-rw-r--r--src/mainboard/supermicro/h8dme/Options.lb260
-rw-r--r--src/mainboard/supermicro/h8dme/apc_auto.c4
-rw-r--r--src/mainboard/supermicro/h8dme/cache_as_ram_auto.c24
-rw-r--r--src/mainboard/supermicro/h8dmr/Config.lb46
-rw-r--r--src/mainboard/supermicro/h8dmr/Options.lb256
-rw-r--r--src/mainboard/supermicro/h8dmr/apc_auto.c4
-rw-r--r--src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c24
-rw-r--r--src/mainboard/supermicro/x6dai_g/Config.lb30
-rw-r--r--src/mainboard/supermicro/x6dai_g/Options.lb150
-rw-r--r--src/mainboard/supermicro/x6dai_g/auto.c2
-rw-r--r--src/mainboard/supermicro/x6dhe_g/Config.lb30
-rw-r--r--src/mainboard/supermicro/x6dhe_g/Options.lb150
-rw-r--r--src/mainboard/supermicro/x6dhe_g/auto.c2
-rw-r--r--src/mainboard/supermicro/x6dhe_g/mptable.c4
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/Config.lb30
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/Options.lb150
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/auto.c2
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/auto.updated.c2
-rw-r--r--src/mainboard/supermicro/x6dhe_g2/mptable.c4
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/Config.lb30
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/Options.lb150
-rw-r--r--src/mainboard/supermicro/x6dhr_ig/auto.c2
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/Config.lb30
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/Options.lb150
-rw-r--r--src/mainboard/supermicro/x6dhr_ig2/auto.c2
26 files changed, 792 insertions, 792 deletions
diff --git a/src/mainboard/supermicro/h8dme/Config.lb b/src/mainboard/supermicro/h8dme/Config.lb
index c3ad78a215..9c07ae9b6f 100644
--- a/src/mainboard/supermicro/h8dme/Config.lb
+++ b/src/mainboard/supermicro/h8dme/Config.lb
@@ -16,8 +16,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/failovercalculation.lb
arch i386 end
@@ -30,30 +30,30 @@ driver mainboard.o
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if CONFIG_USE_INIT
makerule ./auto.o
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
- depends "$(MAINBOARD)/apc_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
@@ -63,13 +63,13 @@ end
##
## Build our 16 bit and 32 bit coreboot entry code
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
@@ -88,8 +88,8 @@ mainboardinit cpu/x86/32bit/entry32.inc
##
## Build our reset vector (This is where coreboot is entered)
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -97,7 +97,7 @@ if HAVE_FAILOVER_BOOT
ldscript /cpu/x86/32bit/reset32.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -115,13 +115,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds
##
## ROMSTRAP table for MCP55
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
@@ -137,12 +137,12 @@ end
### Things are delicate and we test to see if we should
### failover to another image.
###
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
end
diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb
index 643cab37cb..d10e4b3304 100644
--- a/src/mainboard/supermicro/h8dme/Options.lb
+++ b/src/mainboard/supermicro/h8dme/Options.lb
@@ -19,91 +19,91 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses HAVE_LOW_TABLES
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_HAVE_LOW_TABLES
uses CONFIG_MULTIBOOT
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
-
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
uses CONFIG_PCI_64BIT_PREF_MEM
@@ -111,9 +111,9 @@ uses CONFIG_LB_MEM_TOPK
uses CONFIG_AP_CODE_IN_CAR
-uses MEM_TRAIN_SEQ
+uses CONFIG_MEM_TRAIN_SEQ
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
uses CONFIG_USE_PRINTK_IN_CAR
@@ -122,24 +122,24 @@ uses CONFIG_USE_PRINTK_IN_CAR
###
##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
-#default ROM_SIZE=524288
-default ROM_SIZE=0x100000
+#default CONFIG_ROM_SIZE=524288
+default CONFIG_ROM_SIZE=0x100000
-default HAVE_LOW_TABLES = 0
+default CONFIG_HAVE_LOW_TABLES = 0
default CONFIG_MULTIBOOT=0
##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
+#default CONFIG_FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=0x40000
#FALLBACK: 256K-4K
-default FALLBACK_SIZE=0x3f000
+default CONFIG_FALLBACK_SIZE=0x3f000
#FAILOVER: 4K
-default FAILOVER_SIZE=0x01000
+default CONFIG_FAILOVER_SIZE=0x01000
#more 1M for pgtbl
default CONFIG_LB_MEM_TOPK=2048
@@ -147,40 +147,40 @@ default CONFIG_LB_MEM_TOPK=2048
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
## ACPI tables will be included
-default HAVE_ACPI_TABLES=0
+default CONFIG_HAVE_ACPI_TABLES=0
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -191,41 +191,41 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-default SERIAL_CPU_INIT=0
+default CONFIG_SERIAL_CPU_INIT=0
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=0
+default CONFIG_APIC_ID_OFFSET=0x10
+default CONFIG_LIFT_BSP_APIC_ID=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
#1G
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#512M
-#default HW_MEM_HOLE_SIZEK=0x80000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
#Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default HT_CHAIN_UNITID_BASE=0
+default CONFIG_HT_CHAIN_UNITID_BASE=0
#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default HT_CHAIN_END_UNITID_BASE=0x6
+#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
#make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
#only offset for SB chain?, default is yes(1)
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -233,15 +233,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
##
## enable CACHE_AS_RAM specifics
##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0
default CONFIG_AP_CODE_IN_CAR=1
-default MEM_TRAIN_SEQ=1
-default WAIT_BEFORE_CPUS_INIT=1
+default CONFIG_MEM_TRAIN_SEQ=1
+default CONFIG_WAIT_BEFORE_CPUS_INIT=1
##
## Build code to setup a generic IOAPIC
@@ -251,37 +251,37 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="h8dme"
-default MAINBOARD_VENDOR="Supermicro"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
+default CONFIG_MAINBOARD_PART_NUMBER="h8dme"
+default CONFIG_MAINBOARD_VENDOR="Supermicro"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
##
## Coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
##
## Load the payload from the ROM
@@ -297,8 +297,8 @@ default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -314,21 +314,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -340,17 +340,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=9
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=9
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
##
## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
#
diff --git a/src/mainboard/supermicro/h8dme/apc_auto.c b/src/mainboard/supermicro/h8dme/apc_auto.c
index 099b6abd17..442945e9f2 100644
--- a/src/mainboard/supermicro/h8dme/apc_auto.c
+++ b/src/mainboard/supermicro/h8dme/apc_auto.c
@@ -94,8 +94,8 @@ static inline unsigned get_nodes(void)
void hardwaremain(int ret_addr)
{
- struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
- struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+ struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+ struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;
diff --git a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
index a71de8428c..606556ba73 100644
--- a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
+++ b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
@@ -35,7 +35,7 @@
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -53,7 +53,7 @@
// for enable the FAN
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
@@ -72,7 +72,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
@@ -194,7 +194,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#endif
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -263,7 +263,7 @@ normal_image:
);
fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image": /* outputs */
:"a" (bist), "b"(cpu_init_detectedx) /* inputs */
)
@@ -275,14 +275,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-#if HAVE_FAILOVER_BOOT==1
-#if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+#if CONFIG_USE_FAILOVER_IMAGE==1
failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif
#else
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
@@ -293,7 +293,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#define RC0 (2<<8)
#define RC1 (1<<8)
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -315,7 +315,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
};
struct sys_info *sysinfo =
- (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
@@ -326,7 +326,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
uart_init();
@@ -347,7 +347,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex8(bsp_apicid);
print_debug("\r\n");
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
/* dump_smbus_registers(); */
diff --git a/src/mainboard/supermicro/h8dmr/Config.lb b/src/mainboard/supermicro/h8dmr/Config.lb
index 94d91d8810..b8c78b1c9d 100644
--- a/src/mainboard/supermicro/h8dmr/Config.lb
+++ b/src/mainboard/supermicro/h8dmr/Config.lb
@@ -19,8 +19,8 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/failovercalculation.lb
arch i386 end
@@ -33,30 +33,30 @@ driver mainboard.o
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
if CONFIG_USE_INIT
makerule ./auto.o
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-if USE_FAILOVER_IMAGE
+if CONFIG_USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o
- depends "$(MAINBOARD)/apc_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
end
ldscript /arch/i386/init/ldscript_apc.lb
end
@@ -66,13 +66,13 @@ end
##
## Build our 16 bit and 32 bit coreboot entry code
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
@@ -91,8 +91,8 @@ mainboardinit cpu/x86/32bit/entry32.inc
##
## Build our reset vector (This is where coreboot is entered)
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -100,7 +100,7 @@ if HAVE_FAILOVER_BOOT
ldscript /cpu/x86/32bit/reset32.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -118,13 +118,13 @@ ldscript /southbridge/nvidia/mcp55/id.lds
##
## ROMSTRAP table for MCP55
##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/mcp55/romstrap.inc
ldscript /southbridge/nvidia/mcp55/romstrap.lds
end
@@ -140,12 +140,12 @@ end
### Things are delicate and we test to see if we should
### failover to another image.
###
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
+if CONFIG_HAVE_FAILOVER_BOOT
+ if CONFIG_USE_FAILOVER_IMAGE
ldscript /arch/i386/lib/failover_failover.lds
end
else
- if USE_FALLBACK_IMAGE
+ if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
end
diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb
index e65dfca0ed..16c798c2f8 100644
--- a/src/mainboard/supermicro/h8dmr/Options.lb
+++ b/src/mainboard/supermicro/h8dmr/Options.lb
@@ -19,89 +19,89 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_ACPI_RESUME
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_ACPI_RESUME
+uses CONFIG_ACPI_SSDTX_NUM
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_USE_FAILOVER_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_FAILOVER_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_FAILOVER_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
-
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
+uses CONFIG_K8_HT_FREQ_1G_SUPPORT
+
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
uses CONFIG_USE_INIT
-uses SERIAL_CPU_INIT
+uses CONFIG_SERIAL_CPU_INIT
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
+uses CONFIG_ENABLE_APIC_EXT_ID
+uses CONFIG_APIC_ID_OFFSET
+uses CONFIG_LIFT_BSP_APIC_ID
uses CONFIG_PCI_64BIT_PREF_MEM
@@ -109,9 +109,9 @@ uses CONFIG_LB_MEM_TOPK
uses CONFIG_AP_CODE_IN_CAR
-uses MEM_TRAIN_SEQ
+uses CONFIG_MEM_TRAIN_SEQ
-uses WAIT_BEFORE_CPUS_INIT
+uses CONFIG_WAIT_BEFORE_CPUS_INIT
uses CONFIG_USE_PRINTK_IN_CAR
@@ -120,21 +120,21 @@ uses CONFIG_USE_PRINTK_IN_CAR
###
##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
-#default ROM_SIZE=524288
-default ROM_SIZE=0x100000
+#default CONFIG_ROM_SIZE=524288
+default CONFIG_ROM_SIZE=0x100000
##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
+#default CONFIG_FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=0x40000
#FALLBACK: 256K-4K
-default FALLBACK_SIZE=0x3f000
+default CONFIG_FALLBACK_SIZE=0x3f000
#FAILOVER: 4K
-default FAILOVER_SIZE=0x01000
+default CONFIG_FAILOVER_SIZE=0x01000
#more 1M for pgtbl
default CONFIG_LB_MEM_TOPK=2048
@@ -142,40 +142,40 @@ default CONFIG_LB_MEM_TOPK=2048
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FAILOVER_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=11
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
## ACPI tables will be included
-default HAVE_ACPI_TABLES=0
+default CONFIG_HAVE_ACPI_TABLES=0
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -186,41 +186,41 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
-default SERIAL_CPU_INIT=0
+default CONFIG_SERIAL_CPU_INIT=0
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=1
+default CONFIG_ENABLE_APIC_EXT_ID=0
+default CONFIG_APIC_ID_OFFSET=0x10
+default CONFIG_LIFT_BSP_APIC_ID=1
#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
#2G
-#default HW_MEM_HOLE_SIZEK=0x200000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
#1G
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#512M
-#default HW_MEM_HOLE_SIZEK=0x80000
+#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
#Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
+default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default HT_CHAIN_UNITID_BASE=0
+default CONFIG_HT_CHAIN_UNITID_BASE=0
#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default HT_CHAIN_END_UNITID_BASE=0x6
+#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
#make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
+default CONFIG_SB_HT_CHAIN_ON_BUS0=2
#only offset for SB chain?, default is yes(1)
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#allow capable device use that above 4G
#default CONFIG_PCI_64BIT_PREF_MEM=1
@@ -228,15 +228,15 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
##
## enable CACHE_AS_RAM specifics
##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc8000
-default DCACHE_RAM_SIZE=0x08000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xc8000
+default CONFIG_DCACHE_RAM_SIZE=0x08000
+default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
default CONFIG_USE_INIT=0
default CONFIG_AP_CODE_IN_CAR=1
-default MEM_TRAIN_SEQ=1
-default WAIT_BEFORE_CPUS_INIT=1
+default CONFIG_MEM_TRAIN_SEQ=1
+default CONFIG_WAIT_BEFORE_CPUS_INIT=1
##
## Build code to setup a generic IOAPIC
@@ -246,37 +246,37 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="h8dmr"
-default MAINBOARD_VENDOR="Supermicro"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
+default CONFIG_MAINBOARD_PART_NUMBER="h8dmr"
+default CONFIG_MAINBOARD_VENDOR="Supermicro"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15d9
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1511
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
##
## Coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00100000
+default CONFIG_RAMBASE=0x00100000
##
## Load the payload from the ROM
@@ -292,8 +292,8 @@ default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -309,21 +309,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -335,17 +335,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
#
diff --git a/src/mainboard/supermicro/h8dmr/apc_auto.c b/src/mainboard/supermicro/h8dmr/apc_auto.c
index 099b6abd17..442945e9f2 100644
--- a/src/mainboard/supermicro/h8dmr/apc_auto.c
+++ b/src/mainboard/supermicro/h8dmr/apc_auto.c
@@ -94,8 +94,8 @@ static inline unsigned get_nodes(void)
void hardwaremain(int ret_addr)
{
- struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
- struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
+ struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
+ struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id;
diff --git a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
index c9b33877b8..34a3bb56eb 100644
--- a/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
+++ b/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
@@ -39,7 +39,7 @@
//if we want to wait for core1 done before DQS training, set it to 0
#define K8_SET_FIDVID_CORE0_ONLY 1
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -57,7 +57,7 @@
// for enable the FAN
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
@@ -76,7 +76,7 @@
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
#include "cpu/x86/bist.h"
@@ -141,7 +141,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#endif
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -212,7 +212,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
);
fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image"
: /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */
@@ -225,21 +225,21 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-#if HAVE_FAILOVER_BOOT==1
- #if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+ #if CONFIG_USE_FAILOVER_IMAGE==1
failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif
#else
- #if USE_FALLBACK_IMAGE == 1
+ #if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
#endif
}
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -252,7 +252,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
};
- struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
@@ -263,7 +263,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
uart_init();
@@ -278,7 +278,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
diff --git a/src/mainboard/supermicro/x6dai_g/Config.lb b/src/mainboard/supermicro/x6dai_g/Config.lb
index 2a144eb96a..8acd71c724 100644
--- a/src/mainboard/supermicro/x6dai_g/Config.lb
+++ b/src/mainboard/supermicro/x6dai_g/Config.lb
@@ -1,10 +1,10 @@
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
include /config/nofailovercalculation.lb
##
@@ -18,30 +18,30 @@ arch i386 end
##
driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
diff --git a/src/mainboard/supermicro/x6dai_g/Options.lb b/src/mainboard/supermicro/x6dai_g/Options.lb
index 576cdb8c3e..68562efad4 100644
--- a/src/mainboard/supermicro/x6dai_g/Options.lb
+++ b/src/mainboard/supermicro/x6dai_g/Options.lb
@@ -1,57 +1,57 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_BTEXT
uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
###
@@ -59,14 +59,14 @@ uses OBJCOPY
###
##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
-default ROM_SIZE=1048576
+default CONFIG_ROM_SIZE=1048576
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
@@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=16
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=16
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="X6DAI"
-default MAINBOARD_VENDOR= "Supermicro"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
+default CONFIG_MAINBOARD_PART_NUMBER="X6DAI"
+default CONFIG_MAINBOARD_VENDOR= "Supermicro"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6780
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
##
## Coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -209,17 +209,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
##
## Don't enable the btext console
diff --git a/src/mainboard/supermicro/x6dai_g/auto.c b/src/mainboard/supermicro/x6dai_g/auto.c
index 078296df42..701fcd6484 100644
--- a/src/mainboard/supermicro/x6dai_g/auto.c
+++ b/src/mainboard/supermicro/x6dai_g/auto.c
@@ -84,7 +84,7 @@ static void main(unsigned long bist)
outb(0x87,0x2e);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/mainboard/supermicro/x6dhe_g/Config.lb b/src/mainboard/supermicro/x6dhe_g/Config.lb
index d972ff1ed2..78be06df0b 100644
--- a/src/mainboard/supermicro/x6dhe_g/Config.lb
+++ b/src/mainboard/supermicro/x6dhe_g/Config.lb
@@ -1,10 +1,10 @@
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
include /config/nofailovercalculation.lb
## Set all of the defaults for an x86 architecture
@@ -17,31 +17,31 @@ arch i386 end
##
driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
diff --git a/src/mainboard/supermicro/x6dhe_g/Options.lb b/src/mainboard/supermicro/x6dhe_g/Options.lb
index bd31e7c14c..47eac1d624 100644
--- a/src/mainboard/supermicro/x6dhe_g/Options.lb
+++ b/src/mainboard/supermicro/x6dhe_g/Options.lb
@@ -1,57 +1,57 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_BTEXT
uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
###
@@ -59,14 +59,14 @@ uses OBJCOPY
###
##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
-default ROM_SIZE=1048576
+default CONFIG_ROM_SIZE=1048576
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
@@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=16
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=16
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="X6DHE_g"
-default MAINBOARD_VENDOR= "Supermicro"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
+default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g"
+default CONFIG_MAINBOARD_VENDOR= "Supermicro"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
##
## Coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -209,17 +209,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
##
## Don't enable the btext console
diff --git a/src/mainboard/supermicro/x6dhe_g/auto.c b/src/mainboard/supermicro/x6dhe_g/auto.c
index da340b73eb..ef99677af7 100644
--- a/src/mainboard/supermicro/x6dhe_g/auto.c
+++ b/src/mainboard/supermicro/x6dhe_g/auto.c
@@ -102,7 +102,7 @@ static void main(unsigned long bist)
outb(0x87,0x2e);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index 6a284981b0..ea8f3590a5 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -109,7 +109,7 @@ void *smp_write_config_table(void *v)
}
else {
printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
- printk_debug("DEBUG: Dev= %p\n", dev);
+ printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
}
/* PXHd apic 5 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
@@ -121,7 +121,7 @@ void *smp_write_config_table(void *v)
}
else {
printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
- printk_debug("DEBUG: Dev= %p\n", dev);
+ printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
}
}
diff --git a/src/mainboard/supermicro/x6dhe_g2/Config.lb b/src/mainboard/supermicro/x6dhe_g2/Config.lb
index 7a5fcdf933..a4950d33ef 100644
--- a/src/mainboard/supermicro/x6dhe_g2/Config.lb
+++ b/src/mainboard/supermicro/x6dhe_g2/Config.lb
@@ -1,10 +1,10 @@
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
include /config/nofailovercalculation.lb
## Set all of the defaults for an x86 architecture
@@ -17,31 +17,31 @@ arch i386 end
##
driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
diff --git a/src/mainboard/supermicro/x6dhe_g2/Options.lb b/src/mainboard/supermicro/x6dhe_g2/Options.lb
index bd31e7c14c..47eac1d624 100644
--- a/src/mainboard/supermicro/x6dhe_g2/Options.lb
+++ b/src/mainboard/supermicro/x6dhe_g2/Options.lb
@@ -1,57 +1,57 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_BTEXT
uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
###
@@ -59,14 +59,14 @@ uses OBJCOPY
###
##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
-default ROM_SIZE=1048576
+default CONFIG_ROM_SIZE=1048576
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
@@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=16
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=16
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="X6DHE_g"
-default MAINBOARD_VENDOR= "Supermicro"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
+default CONFIG_MAINBOARD_PART_NUMBER="X6DHE_g"
+default CONFIG_MAINBOARD_VENDOR= "Supermicro"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6080
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
##
## Coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -209,17 +209,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
##
## Don't enable the btext console
diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.c b/src/mainboard/supermicro/x6dhe_g2/auto.c
index 0622ab7ade..4a3029f9aa 100644
--- a/src/mainboard/supermicro/x6dhe_g2/auto.c
+++ b/src/mainboard/supermicro/x6dhe_g2/auto.c
@@ -103,7 +103,7 @@ static void main(unsigned long bist)
outb(0x87,0x2e);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- pc87427_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+ pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c
index fcf8b76c19..8de5a2723b 100644
--- a/src/mainboard/supermicro/x6dhe_g2/auto.updated.c
+++ b/src/mainboard/supermicro/x6dhe_g2/auto.updated.c
@@ -103,7 +103,7 @@ static void main(unsigned long bist)
outb(0x87,0x2e);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index 6a284981b0..ea8f3590a5 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -109,7 +109,7 @@ void *smp_write_config_table(void *v)
}
else {
printk_debug("ERROR - could not find IOAPIC PCI 1:00.1\n");
- printk_debug("DEBUG: Dev= %p\n", dev);
+ printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
}
/* PXHd apic 5 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
@@ -121,7 +121,7 @@ void *smp_write_config_table(void *v)
}
else {
printk_debug("ERROR - could not find IOAPIC PCI 1:00.3\n");
- printk_debug("DEBUG: Dev= %p\n", dev);
+ printk_debug("CONFIG_DEBUG: Dev= %p\n", dev);
}
}
diff --git a/src/mainboard/supermicro/x6dhr_ig/Config.lb b/src/mainboard/supermicro/x6dhr_ig/Config.lb
index 837beb45f4..7d70dcf5db 100644
--- a/src/mainboard/supermicro/x6dhr_ig/Config.lb
+++ b/src/mainboard/supermicro/x6dhr_ig/Config.lb
@@ -1,10 +1,10 @@
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
include /config/nofailovercalculation.lb
##
@@ -18,30 +18,30 @@ arch i386 end
##
driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
diff --git a/src/mainboard/supermicro/x6dhr_ig/Options.lb b/src/mainboard/supermicro/x6dhr_ig/Options.lb
index 808fe21018..b6f853242a 100644
--- a/src/mainboard/supermicro/x6dhr_ig/Options.lb
+++ b/src/mainboard/supermicro/x6dhr_ig/Options.lb
@@ -1,57 +1,57 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_BTEXT
uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
###
@@ -59,14 +59,14 @@ uses OBJCOPY
###
##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
-default ROM_SIZE=1048576
+default CONFIG_ROM_SIZE=1048576
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
@@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=16
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=16
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="X6DHR"
-default MAINBOARD_VENDOR= "Supermicro"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
+default CONFIG_MAINBOARD_PART_NUMBER="X6DHR"
+default CONFIG_MAINBOARD_VENDOR= "Supermicro"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
##
## Coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -209,17 +209,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
##
## Don't enable the btext console
diff --git a/src/mainboard/supermicro/x6dhr_ig/auto.c b/src/mainboard/supermicro/x6dhr_ig/auto.c
index 92020189d2..722157b454 100644
--- a/src/mainboard/supermicro/x6dhr_ig/auto.c
+++ b/src/mainboard/supermicro/x6dhr_ig/auto.c
@@ -103,7 +103,7 @@ static void main(unsigned long bist)
outb(0x87,0x2e);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Config.lb b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
index b223a37523..4aab4fb04b 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/Config.lb
+++ b/src/mainboard/supermicro/x6dhr_ig2/Config.lb
@@ -1,10 +1,10 @@
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 128 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
include /config/nofailovercalculation.lb
##
@@ -18,30 +18,30 @@ arch i386 end
##
driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
##
## Romcc output
##
makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+ action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
end
##
@@ -55,7 +55,7 @@ ldscript /cpu/x86/32bit/entry32.lds
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -77,7 +77,7 @@ ldscript /arch/i386/lib/id.lds
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc
end
diff --git a/src/mainboard/supermicro/x6dhr_ig2/Options.lb b/src/mainboard/supermicro/x6dhr_ig2/Options.lb
index 808fe21018..b6f853242a 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/Options.lb
+++ b/src/mainboard/supermicro/x6dhr_ig2/Options.lb
@@ -1,57 +1,57 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_LOGICAL_CPUS
uses CONFIG_MAX_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
uses CONFIG_UDELAY_TSC
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses _RAMBASE
+uses CONFIG_RAMBASE
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_SERIAL8250
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_BTEXT
uses CC
-uses HOSTCC
-uses CROSS_COMPILE
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
###
@@ -59,14 +59,14 @@ uses OBJCOPY
###
##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
-default ROM_SIZE=1048576
+default CONFIG_ROM_SIZE=1048576
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Delay timer options
@@ -78,31 +78,31 @@ default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=16
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=16
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -120,39 +120,39 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="X6DHR"
-default MAINBOARD_VENDOR= "Supermicro"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
+default CONFIG_MAINBOARD_PART_NUMBER="X6DHR"
+default CONFIG_MAINBOARD_VENDOR= "Supermicro"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 32K heap
##
-default HEAP_SIZE=0x8000
+default CONFIG_HEAP_SIZE=0x8000
###
### Compute the location and size of where this firmware image
### (coreboot plus bootloader) will live in the boot rom chip.
###
-default FALLBACK_SIZE=131072
+default CONFIG_FALLBACK_SIZE=131072
##
## Coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -167,8 +167,8 @@ default CONFIG_ROM_PAYLOAD=1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -183,21 +183,21 @@ default CONFIG_GDB_STUB=0
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -209,17 +209,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
##
## Don't enable the btext console
diff --git a/src/mainboard/supermicro/x6dhr_ig2/auto.c b/src/mainboard/supermicro/x6dhr_ig2/auto.c
index 7be6250650..97eaca3a63 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/auto.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/auto.c
@@ -103,7 +103,7 @@ static void main(unsigned long bist)
outb(0x87,0x2e);
outb(0x87,0x2e);
pnp_write_config(CONSOLE_SERIAL_DEV, 0x24, 0x84 | (1 << 6));
- w83627hf_enable_dev(CONSOLE_SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();