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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 14:46:47 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-12 09:58:33 +0000
commit45f448f4a4e09b270d964c98d3aced2e73d9d6bc (patch)
treed217f38c8a28fbf1c449f17f243b73a7f23db6dd /src/mainboard/supermicro
parentc05c2b3fb25ca42a75ecc987178c298f7fe0ead5 (diff)
downloadcoreboot-45f448f4a4e09b270d964c98d3aced2e73d9d6bc.tar.xz
haswell: Relocate `mainboard_romstage_entry` to northbridge
This is what sandybridge does, and if done properly allows factoring out common settings. Said refactoring will be handled in subsequent commits. Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/supermicro')
-rw-r--r--src/mainboard/supermicro/x10slm-f/romstage.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index 2e3f42e7f1..6c122661d9 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/intel/haswell/haswell.h>
-#include <arch/romstage.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/pei_data.h>
+#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <stdint.h>
@@ -20,9 +20,9 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
}
-void mainboard_romstage_entry(void)
+void mainboard_fill_pei_data(struct pei_data *pei_data)
{
- struct pei_data pei_data = {
+ struct pei_data mainboard_pei_data = {
.pei_version = PEI_VERSION,
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
@@ -68,5 +68,5 @@ void mainboard_romstage_entry(void)
},
};
- romstage_common(&pei_data);
+ *pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
}