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authorNico Huber <nico.h@gmx.de>2019-10-12 15:16:33 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:01:00 +0000
commit9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7 (patch)
tree68af4367507ca483522d2013b64c3e2e83511b67 /src/mainboard/system76/lemp9
parent95dcf29b2fcc9f7c02812d760ec0be492d5b7580 (diff)
downloadcoreboot-9ea70c02cd0e5e28f38136ebbb6dbad72ad177c7.tar.xz
intel/cannonlake: Implement PCIe RP devicetree update
Some existing devicetrees were manually adapted to anticipate root-port switching. Now, their PCI-device on/off settings should just reflect the `PcieRpEnable` state and configuration happens on the PCI function that was assigned at reset. Change-Id: I4d76f38c222b74053c6a2f80b492d4660ab4db6d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/system76/lemp9')
-rw-r--r--src/mainboard/system76/lemp9/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index 3fa2c170e3..6cf0fff9de 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -207,7 +207,7 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
- device pci 1c.0 on end # PCI Express Port 1
+ device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4