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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-18 00:46:51 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-20 21:32:50 +0000 |
| commit | 3f5bfbd4d1a963a6c1266b83fac2f1abc781b321 (patch) | |
| tree | 81f86e88e645053f891129ef99fc2a3e2c793644 /src/mainboard/system76 | |
| parent | 80bd8e43b04b21acd1f989779a59e0d69b2158c1 (diff) | |
| download | coreboot-3f5bfbd4d1a963a6c1266b83fac2f1abc781b321.tar.xz | |
mb/system76/lemp9: move LPC options to the devicetree
Change-Id: I7b7acdc51c848541fb39926bc8de1115c026dd05
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45496
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/system76')
| -rw-r--r-- | src/mainboard/system76/lemp9/devicetree.cb | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 12d90d113e..b1899417b9 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -50,17 +50,6 @@ chip soc/intel/cannonlake # Thermal register "tcc_offset" = "12" -# LPC (soc/intel/cannonlake/lpc.c) - # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x84: Decode 0x80 - 0x8F (Port 80) - register "gen1_dec" = "0x000c0081" - # Address 0x88: Decode 0x68 - 0x6F (PMC) - register "gen2_dec" = "0x00040069" - # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen3_dec" = "0x00fc0E01" - # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen4_dec" = "0x00fc0F01" - # PM Util (soc/intel/cannonlake/pmutil.c) # GPE configuration # Note that GPE events called out in ASL code rely on this @@ -193,6 +182,15 @@ chip soc/intel/cannonlake device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 device pci 1f.0 on # LPC Interface + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x80 - 0x8F (Port 80) + register "gen1_dec" = "0x000c0081" + # Address 0x88: Decode 0x68 - 0x6F (PMC) + register "gen2_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen3_dec" = "0x00fc0E01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen4_dec" = "0x00fc0F01" chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end |