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authorFelix Singer <felixsinger@posteo.net>2020-09-05 05:16:44 +0000
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-09-07 12:32:58 +0000
commit4ca3873457dc6be2fb7b77e017e5d1f41143a496 (patch)
treeea731e1696566077201de70f791c307c1118cde5 /src/mainboard/system76
parent63b9e791bc2462009394625a84b889dacd60e4c0 (diff)
downloadcoreboot-4ca3873457dc6be2fb7b77e017e5d1f41143a496.tar.xz
mb/system76/lemp9: Enable SataPortsDevSlp
Enable SataPortsDevSlp for SATA ports 2 and 3. Change-Id: Id6c69f4a6fe45cb5c6aad3f42c741a2724c6166c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src/mainboard/system76')
-rw-r--r--src/mainboard/system76/lemp9/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index f0cee063e7..6bece6d047 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -178,7 +178,9 @@ chip soc/intel/cannonlake
register "SataMode" = "Sata_AHCI"
register "SataSalpSupport" = "0"
register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[1]" = "1"
register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5