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| author | Patrick Georgi <patrick@georgi-clan.de> | 2010-11-20 10:31:00 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-11-20 10:31:00 +0000 |
| commit | 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a (patch) | |
| tree | 325b7b6abc1d4514d52ad1f726d9be4fa00d0454 /src/mainboard/technexion/tim5690 | |
| parent | 622824cadbbbe003bc3e8c97694d2cf6bae0de9b (diff) | |
| download | coreboot-9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a.tar.xz | |
Unify DIMM SPD addressing. For Geode, change the
addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).
abuild tested.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/technexion/tim5690')
| -rw-r--r-- | src/mainboard/technexion/tim5690/romstage.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 05ce74da3a..de86013b5d 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -20,9 +20,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include <stdint.h> @@ -39,6 +36,7 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" |