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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-11-06 17:11:05 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-11-06 17:11:05 +0000 |
| commit | d63085b20ef40caae1c60a7532b5243e1e30b109 (patch) | |
| tree | c732b7666d8082775022592eeddedff81375eeef /src/mainboard/technexion/tim5690 | |
| parent | eeec0ef00a6be64d6846599fe7cf81ead22e2f02 (diff) | |
| download | coreboot-d63085b20ef40caae1c60a7532b5243e1e30b109.tar.xz | |
Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/technexion/tim5690')
| -rw-r--r-- | src/mainboard/technexion/tim5690/Config.lb | 9 | ||||
| -rw-r--r-- | src/mainboard/technexion/tim5690/devicetree.cb | 9 |
2 files changed, 0 insertions, 18 deletions
diff --git a/src/mainboard/technexion/tim5690/Config.lb b/src/mainboard/technexion/tim5690/Config.lb index d46aa3ba61..d400a2d6c9 100644 --- a/src/mainboard/technexion/tim5690/Config.lb +++ b/src/mainboard/technexion/tim5690/Config.lb @@ -134,7 +134,6 @@ config chip.h #The variables belong to mainboard are defined here. #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -158,10 +157,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" #512KB - #register "rom_address" = "0xfff00000" #1024KB - #register "rom_address" = "0xffe00000" #2048KB - #register "rom_address" = "0xffc00000" #4096KB end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -171,10 +166,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" - #register "vga_rom_address" = "0xfff00000" - #register "vga_rom_address" = "0xffe00000" - #register "vga_rom_address" = "0xffc00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb index fb95aad887..8bd6fe1f9d 100644 --- a/src/mainboard/technexion/tim5690/devicetree.cb +++ b/src/mainboard/technexion/tim5690/devicetree.cb @@ -1,5 +1,4 @@ #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define vga_rom_address = 0xfff80000 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, # 1: the system allows a PCIE link to be established on Dev2 or Dev3. @@ -23,10 +22,6 @@ chip northbridge/amd/amdk8/root_complex device pci 1.0 on # Internal Graphics P2P bridge 0x7912 chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F - register "rom_address" = "0xfff80000" #512KB - #register "rom_address" = "0xfff00000" #1024KB - #register "rom_address" = "0xffe00000" #2048KB - #register "rom_address" = "0xffc00000" #4096KB end end device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 @@ -36,10 +31,6 @@ chip northbridge/amd/amdk8/root_complex device pci 6.0 on end # PCIE P2P bridge 0x7916 device pci 7.0 on end # PCIE P2P bridge 0x7917 device pci 8.0 off end # NB/SB Link P2P bridge - register "vga_rom_address" = "0xfff80000" - #register "vga_rom_address" = "0xfff00000" - #register "vga_rom_address" = "0xffe00000" - #register "vga_rom_address" = "0xffc00000" register "gpp_configuration" = "4" register "port_enable" = "0xfc" register "gfx_dev2_dev3" = "1" |