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| author | Patrick Georgi <patrick@georgi-clan.de> | 2012-05-05 15:29:32 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-05-08 00:34:34 +0200 |
| commit | e166782f397f7db2c4446c5e120fa30afbde7bdd (patch) | |
| tree | fac736e744d9ec6d49e321e63971277e611d2000 /src/mainboard/technexion/tim8690 | |
| parent | fe4221848f86ab97d2c439299826d97e48542404 (diff) | |
| download | coreboot-e166782f397f7db2c4446c5e120fa30afbde7bdd.tar.xz | |
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
(and some manual changes to fix false positives)
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Diffstat (limited to 'src/mainboard/technexion/tim8690')
| -rw-r--r-- | src/mainboard/technexion/tim8690/get_bus_conf.c | 4 | ||||
| -rw-r--r-- | src/mainboard/technexion/tim8690/mainboard.c | 4 | ||||
| -rw-r--r-- | src/mainboard/technexion/tim8690/mptable.c | 2 | ||||
| -rw-r--r-- | src/mainboard/technexion/tim8690/romstage.c | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c index 2b0fca7abf..d4152a1314 100644 --- a/src/mainboard/technexion/tim8690/get_bus_conf.c +++ b/src/mainboard/technexion/tim8690/get_bus_conf.c @@ -23,7 +23,7 @@ #include <string.h> #include <stdint.h> #include <stdlib.h> -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS #include <cpu/amd/multicore.h> #endif @@ -107,7 +107,7 @@ void get_bus_conf(void) } /* I/O APICs: APIC ID Version State Address */ -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS apicid_base = get_apicid_base(1); #else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 664372d879..18abbc930d 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -147,7 +147,7 @@ static void tim8690_enable(device_t dev) { printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA msr_t msr, msr2; /* TOP_MEM: the top of DRAM below 4G */ @@ -197,7 +197,7 @@ int add_mainboard_resources(struct lb_memory *mem) /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ -#if (CONFIG_GFXUMA == 1) +#if CONFIG_GFXUMA printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 4ffba6f310..bb3232a1cf 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v) /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#if CONFIG_GENERATE_ACPI_TABLES == 0 +#if !CONFIG_GENERATE_ACPI_TABLES #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) #else diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 97bc4e1ddd..875321e519 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); |