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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-03-18 16:18:58 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-03-18 16:18:58 +0000
commit776b85ba457ff82f795c6c65b5574ef27e611097 (patch)
treeba3ddce3ac37c4edb8e3105390e4de959eba3ca9 /src/mainboard/technexion/tim8690
parenta41b939294c2e90197c57a2faa565bf48d4b506d (diff)
downloadcoreboot-776b85ba457ff82f795c6c65b5574ef27e611097.tar.xz
Remove fallback/normal handling in mainboards'
romstage.c like r5255 did for failover/fallback/normal mainboards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/technexion/tim8690')
-rw-r--r--src/mainboard/technexion/tim8690/romstage.c59
1 files changed, 9 insertions, 50 deletions
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index ff86ba3713..a101b1a495 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -100,60 +100,10 @@ static inline int spd_read_byte(u32 device, u32 address)
#include "cpu/amd/model_fxx/fidvid.c"
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-
#include "northbridge/amd/amdk8/early_ht.c"
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- /* Is this a cpu only reset? Is this a secondary cpu? */
- if ((cpu_init_detectedx) || (!boot_cpu())) {
- if (last_boot_normal()) { /* RTC already inited */
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* sb600_lpc_port80(); */
- sb600_pci_port80();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
-normal_image:
- post_code(0x23);
- __asm__ volatile ("jmp __normal_image": /* outputs */
- :"a" (bist), "b"(cpu_init_detectedx) /* inputs */);
-
-fallback_image:
- post_code(0x25);
-}
-#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
-#if CONFIG_USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
-#endif
- real_main(bist, cpu_init_detectedx);
-}
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
@@ -162,6 +112,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ enumerate_ht_chain();
+
+ /* sb600_lpc_port80(); */
+ sb600_pci_port80();
+ }
+
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}