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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-28 11:50:10 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2017-04-27 10:18:28 +0200 |
| commit | fb2f667da2091ce2194274f95c2d5db024d46e63 (patch) | |
| tree | 5c9c72faf4d1279a5c6b64ca2ae8a1a879ac84aa /src/mainboard/technexion | |
| parent | c0f7a1b7d12062595f01442989e4eac2869e5b7a (diff) | |
| download | coreboot-fb2f667da2091ce2194274f95c2d5db024d46e63.tar.xz | |
nb/amd/amdk8: Link raminit_f.c
For this debug.c needs to be linked too.
Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/technexion')
| -rw-r--r-- | src/mainboard/technexion/tim5690/romstage.c | 9 | ||||
| -rw-r--r-- | src/mainboard/technexion/tim8690/romstage.c | 9 |
2 files changed, 8 insertions, 10 deletions
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index e534617e4d..4ffafb11df 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -27,7 +27,7 @@ #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/x86/bist.h> @@ -38,17 +38,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index d5a4784ced..7f41536277 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,7 @@ #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/x86/bist.h> @@ -39,17 +39,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" |