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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-09-22 09:43:25 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-09-22 09:43:25 +0000
commit513e03bd96b9c2d2c3a9ad10961de4f76586ace3 (patch)
tree1e355e1912744adb43d25a9896388907e5b071d7 /src/mainboard/technexion
parent00003ae7129802d7f943756c94b35372c1b1b053 (diff)
downloadcoreboot-513e03bd96b9c2d2c3a9ad10961de4f76586ace3.tar.xz
r4646 enabled early usage of pci_{read,write}_config{8,16,32}
This allows us to change dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x64); to the much more readable dword = pci_read_config32(sm_dev, 0x64); Clean up all PCI operations in mainboards based on AMD 690: amd/pistachio amd/dbm690t technexion/tim8690 Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/technexion')
-rw-r--r--src/mainboard/technexion/tim8690/mainboard.c17
1 files changed, 6 insertions, 11 deletions
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 3bb3cf40e5..30a4bc8a97 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -59,16 +59,15 @@ static void enable_onboard_nic()
u8 byte;
device_t sm_dev;
- struct bus pbus;
printk_info("enable_onboard_nic.\n");
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- byte= pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a);
+ byte = pci_read_config8(sm_dev, 0x9a);
byte |= ( 1 << 7);
- pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0x9a,byte);
+ pci_write_config8(sm_dev, 0x9a, byte);
byte=pm_ioread(0x59);
@@ -76,10 +75,10 @@ static void enable_onboard_nic()
pm_iowrite(0x59,byte);
- byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8);
+ byte = pci_read_config8(sm_dev, 0xA8);
byte |= (1 << 1); //set bit 1 to high
- pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn, 0xA8, byte);
+ pci_write_config8(sm_dev, 0xA8, byte);
}
/* set thermal config
@@ -89,7 +88,6 @@ static void set_thermal_config()
u8 byte;
u16 word;
device_t sm_dev;
- struct bus pbus;
/* set ADT 7461 */
ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
@@ -112,12 +110,9 @@ static void set_thermal_config()
/* set GPIO 64 to input */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- word =
- pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x56);
+ word = pci_read_config16(sm_dev, 0x56);
word |= 1 << 7;
- pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
- sm_dev->path.pci.devfn, 0x56, word);
+ pci_write_config16(sm_dev, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);