summaryrefslogtreecommitdiff
path: root/src/mainboard/technexion
diff options
context:
space:
mode:
authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-04-27 00:41:50 +1000
committerRudolf Marek <r.marek@assembler.cz>2014-05-11 17:52:08 +0200
commitf29200240e428761827ab8d179fa23068bfa9d59 (patch)
treee8f20cf76e224a08152c46196894479bd6105436 /src/mainboard/technexion
parent946bee1c349db6bf88b4f6736dc910eb4890a74b (diff)
downloadcoreboot-f29200240e428761827ab8d179fa23068bfa9d59.tar.xz
superio/ite/*: Factor out generic romstage component
Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5585 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/mainboard/technexion')
-rw-r--r--src/mainboard/technexion/tim5690/romstage.c8
-rw-r--r--src/mainboard/technexion/tim8690/romstage.c8
2 files changed, 10 insertions, 6 deletions
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index e6483c0e21..35351b1266 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -32,12 +32,15 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -85,8 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs690_dev8();
sb600_lpc_init();
- /* it8712f_enable_serial does not use its 1st parameter. */
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 2f3ad71562..7455df2327 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -32,12 +32,15 @@
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
-#include "superio/ite/it8712f/early_serial.c"
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8712f/it8712f.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include "southbridge/amd/rs690/early_setup.c"
#include "southbridge/amd/sb600/early_setup.c"
+#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
+
static void memreset(int controllers, const struct mem_controller *ctrl) { }
static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs690_dev8();
sb600_lpc_init();
- /* it8712f_enable_serial does not use its 1st parameter. */
- it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
it8712f_kill_watchdog();
console_init();