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authorJoseph Smith <joe@settoplinux.org>2010-04-09 11:10:25 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-09 11:10:25 +0000
commit7488e049df9899dd7062b2ffe393b3e9a6f50dc5 (patch)
treea226c1f16a9220abb947ba46d26570e065494aa5 /src/mainboard/thomson
parent853263b963b4cacb4f7fa3a7f2c68dcbd094f1d7 (diff)
downloadcoreboot-7488e049df9899dd7062b2ffe393b3e9a6f50dc5.tar.xz
1. This patch adds CAR for Intel P6 series processors.
2. Add support for Micro-FCBGA 479 Celeron and PIII's 3. Add support for model_6bx and microcode updates 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000 Build and boot tested. Signed-off-by: Joseph Smith <joe@settoplinux.org> The change to CAR reveiled a few more warnings in the ICH4 and i830 code, I fixed them on the fly. Checking this in because my last two commits broke Joseph's CAR patch. This version fixes the issues. Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/thomson')
-rw-r--r--src/mainboard/thomson/ip1000/Kconfig16
-rw-r--r--src/mainboard/thomson/ip1000/Makefile.inc2
-rw-r--r--src/mainboard/thomson/ip1000/devicetree.cb2
-rw-r--r--src/mainboard/thomson/ip1000/romstage.c6
4 files changed, 18 insertions, 8 deletions
diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig
index 56ebee77b7..9934d0be36 100644
--- a/src/mainboard/thomson/ip1000/Kconfig
+++ b/src/mainboard/thomson/ip1000/Kconfig
@@ -1,18 +1,20 @@
config BOARD_THOMSON_IP1000
bool "IP1000"
select ARCH_X86
- select CPU_INTEL_SOCKET_PGA370
+ select CPU_INTEL_SOCKET_MFCBGA479
select NORTHBRIDGE_INTEL_I82830
select SOUTHBRIDGE_INTEL_I82801DX
select SUPERIO_SMSC_SMSCSUPERIO
- select ROMCC
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select HAVE_HARD_RESET
select HAVE_MAINBOARD_RESOURCES
+ select USE_PRINTK_IN_CAR
select HAVE_SMI_HANDLER
select GFXUMA
+ select USE_DCACHE_RAM
+ select TINY_BOOTBLOCK
config MAINBOARD_DIR
string
@@ -29,6 +31,16 @@ config HAVE_OPTION_TABLE
default n
depends on BOARD_THOMSON_IP1000
+config DCACHE_RAM_BASE
+ hex
+ default 0xffdf8000
+ depends on BOARD_THOMSON_IP1000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on BOARD_THOMSON_IP1000
+
config IRQ_SLOT_COUNT
int
default 7
diff --git a/src/mainboard/thomson/ip1000/Makefile.inc b/src/mainboard/thomson/ip1000/Makefile.inc
index 38a5a61fdd..6c034c0e1f 100644
--- a/src/mainboard/thomson/ip1000/Makefile.inc
+++ b/src/mainboard/thomson/ip1000/Makefile.inc
@@ -1,4 +1,2 @@
-ROMCCFLAGS=-mcpu=p3 -O
-
smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb
index a3ee26cc59..a2b5fe87af 100644
--- a/src/mainboard/thomson/ip1000/devicetree.cb
+++ b/src/mainboard/thomson/ip1000/devicetree.cb
@@ -1,6 +1,6 @@
chip northbridge/intel/i82830 # Northbridge
device apic_cluster 0 on # APIC cluster
- chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479
+ chip cpu/intel/socket_mFCBGA479 # Low Voltage PIII Micro-FCBGA Socket 479
device apic 0 on end # APIC
end
end
diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
index 4a8e0a698a..5c49f615b3 100644
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ b/src/mainboard/thomson/ip1000/romstage.c
@@ -35,7 +35,6 @@
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/i82801dx_reset.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "spd_table.h"
#include "gpio.c"
@@ -97,10 +96,11 @@ static void mb_early_setup(void)
pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
}
-static void main(unsigned long bist)
+#include "cpu/intel/model_6bx/cache_as_ram_disable.c"
+
+void real_main(unsigned long bist)
{
if (bist == 0) {
- early_mtrr_init();
if (memory_initialized()) {
hard_reset();
}