diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2009-11-06 17:11:05 +0000 |
---|---|---|
committer | Myles Watson <mylesgw@gmail.com> | 2009-11-06 17:11:05 +0000 |
commit | d63085b20ef40caae1c60a7532b5243e1e30b109 (patch) | |
tree | c732b7666d8082775022592eeddedff81375eeef /src/mainboard/thomson | |
parent | eeec0ef00a6be64d6846599fe7cf81ead22e2f02 (diff) | |
download | coreboot-d63085b20ef40caae1c60a7532b5243e1e30b109.tar.xz |
Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/thomson')
-rw-r--r-- | src/mainboard/thomson/ip1000/Config.lb | 1 | ||||
-rw-r--r-- | src/mainboard/thomson/ip1000/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/thomson/ip1000/Config.lb b/src/mainboard/thomson/ip1000/Config.lb index 00c913cfcc..8eaa606ac4 100644 --- a/src/mainboard/thomson/ip1000/Config.lb +++ b/src/mainboard/thomson/ip1000/Config.lb @@ -77,7 +77,6 @@ chip northbridge/intel/i82830 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb index c3e0e7f8fe..aa0f3f93da 100644 --- a/src/mainboard/thomson/ip1000/devicetree.cb +++ b/src/mainboard/thomson/ip1000/devicetree.cb @@ -3,7 +3,6 @@ chip northbridge/intel/i82830 # Northbridge device pci 0.0 on end # Host bridge chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC) - register "rom_address" = "0xfff00000" end chip southbridge/intel/i82801xx # Southbridge register "pirqa_routing" = "0x05" |